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32-Bit TX System RISC TX39 Family TMPR3916
MIPS16, application Specific Extensions and R3000A are a trademark of MIPS Technologies, Inc. The information contained herein is subject to change without notice. The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. The products described in this document contain components made in the United States and subject to export control of the U.S. authorities. Diversion contrary to the U.S. law is prohibited. TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. The Toshiba products listed in this document are intended for usage in general electronics applications ( computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These Toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of Toshiba products listed in this document shall be made at the customer's own risk. The products described in this document may include products subject to the foreign exchange and foreign trade laws.
(c) 2002 TOSHIBA CORPORATION All Rights Reserved
Preface
This document describes the basic functions of TMPR3916F "Capricorn2". This document is meant to provide all information, which is needed to program and operate the device from a software developer's point of view.
October 2002
TMPR3916
Table of Contents
Handling precautions TMPR3916 1. The TMPR3916.......................................................................................................................................................1-1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 1.10 2.1 2.2 2.3 2.4 2.5 2.6 3.1 3.2 3.3 3.4 3.5 4.1 4.2 4.3 5.1 5.2 6.1 6.2 7.1 7.2 7.3 7.4 7.5 Applications and References ..........................................................................................................................1-1 Features...........................................................................................................................................................1-2 Differences Between TX3903AF and TMPR3916.........................................................................................1-3 Structure of TMPR3916 and a System Example ............................................................................................1-4 Address Map...................................................................................................................................................1-6 Clocks .............................................................................................................................................................1-8 Resets..............................................................................................................................................................1-9 Time-Out-Error Control Unit........................................................................................................................1-10 Operating Modes of TMPR3916 ..................................................................................................................1-10 Chip Configuration Register (CCR) .............................................................................................................1-11 Structure of Memory Controller .....................................................................................................................2-2 Example Memory Configuration ....................................................................................................................2-3 Ports of Memory Controller............................................................................................................................2-6 Registers .........................................................................................................................................................2-6 SDRAMC Functions.......................................................................................................................................2-7 MEMC Function...........................................................................................................................................2-20 GDC Structure ................................................................................................................................................3-2 Scrolling .........................................................................................................................................................3-9 Internal Blockdiagram ..................................................................................................................................3-12 Registers .......................................................................................................................................................3-13 Setting Examples ..........................................................................................................................................3-21 Basic Interrupt Handling.................................................................................................................................4-1 Registers .........................................................................................................................................................4-2 Non Maskable Interrupt..................................................................................................................................4-4 PWM Timer ....................................................................................................................................................5-1 Periodic Timers...............................................................................................................................................5-3 Programming the DMA Controller.................................................................................................................6-2 Registers .........................................................................................................................................................6-5 Block Diagram................................................................................................................................................7-2 TXCAN Registers...........................................................................................................................................7-3 TXCAN Interrupt Logic ...............................................................................................................................7-22 TXCAN Operation Modes............................................................................................................................7-25 Handling of Message-Objects.......................................................................................................................7-30
2. Memory Controller (MC) ........................................................................................................................................2-1
3. Graphics Display Controller (GDC)........................................................................................................................3-1
4. Interrupt Controller (INTC).....................................................................................................................................4-1
5. TIMER ....................................................................................................................................................................5-1
6. Direct Memory Access Controller (DMAC) ...........................................................................................................6-1
7. CAN Module (TXCAN)..........................................................................................................................................7-1
8. Parallel Interface (PORT) ........................................................................................................................................8-1
i
TMPR3916
9. Synchronous Serial I/O (TXSEI).............................................................................................................................9-1 9.1 9.2 9.3 9.4 10.1 10.2 10.3 10.4 11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8 11.9 TXSEI Structure .............................................................................................................................................9-2 Registers .........................................................................................................................................................9-3 TXSEI Operations ........................................................................................................................................9-15 Interrupts.......................................................................................................................................................9-19 Operations on Serial Interface ......................................................................................................................10-1 Registers .....................................................................................................................................................10-10 Timings.......................................................................................................................................................10-19 Flow Charts ................................................................................................................................................10-21 DC Characteristics of TMPR3916................................................................................................................11-1 Power Up Sequence......................................................................................................................................11-2 Crystal Oscillator..........................................................................................................................................11-3 View DAC ....................................................................................................................................................11-4 Standby Mode Timing ..................................................................................................................................11-5 Boot Device ..................................................................................................................................................11-5 SDRAM Timing ...........................................................................................................................................11-6 ROM / SRAM Timing ..................................................................................................................................11-7 External Slave...............................................................................................................................................11-8
10. Asynchronous Serial Interface (UART) ................................................................................................................10-1
11. Electrical Characteristics .......................................................................................................................................11-1
11.10 External Interrupts and NMI.......................................................................................................................11-10 11.11 General Purpose I/O (PORT Module) ........................................................................................................11-10 11.12 TXSEI Timing ............................................................................................................................................11-11 12. Package Dimension ...............................................................................................................................................12-1 12.1 12.2 Pin Assignment.............................................................................................................................................12-1 Pin Functions ................................................................................................................................................12-5 Register Overview of TMPR3916 ....................................................................................................A-1
Appendix A.
ii
Handling Precautions
1 Using Toshiba Semiconductors Safely
1.
Using Toshiba Semiconductors Safely
TOSHIBA are continually working to improve the quality and the reliability of their products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook. The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk.
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1 Using Toshiba Semiconductors Safely
1-2
2 Safety Precautions
2.
Safety Precautions
This section lists important precautions which users of semiconductor devices (and anyone else) should observe in order to avoid injury and damage to property, and to ensure safe and correct use of devices. Please be sure that you understand the meanings of the labels and the graphic symbol described below before you move on to the detailed descriptions of the precautions.
[Explanation of labels] Indicates an imminently hazardous situation which will result in death or serious injury if you do not follow instructions. Indicates a potentially hazardous situation which could result in death or serious injury if you do not follow instructions. Indicates a potentially hazardous situation which if not avoided, may result in minor injury or moderate injury.
[Explanation of graphic symbol]
Graphic symbol Meaning
Indicates that caution is required (laser beam is dangerous to eyes).
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2 Safety Precautions
2.1
General Precautions regarding Semiconductor Devices
Do not use devices under conditions exceeding their absolute maximum ratings (e.g. current, voltage, power dissipation or temperature). This may cause the device to break down, degrade its performance, or cause it to catch fire or explode resulting in injury. Do not insert devices in the wrong orientation. Make sure that the positive and negative terminals of power supplies are connected correctly. Otherwise the rated maximum current or power dissipation may be exceeded and the device may break down or undergo performance degradation, causing it to catch fire or explode and resulting in injury. When power to a device is on, do not touch the device's heat sink. Heat sinks become hot, so you may burn your hand. Do not touch the tips of device leads. Because some types of device have leads with pointed tips, you may prick your finger. When conducting any kind of evaluation, inspection or testing, be sure to connect the testing equipment's electrodes or probes to the pins of the device under test before powering it on. Otherwise, you may receive an electric shock causing injury. Before grounding an item of measuring equipment or a soldering iron, check that there is no electrical leakage from it. Electrical leakage may cause the device which you are testing or soldering to break down, or could give you an electric shock. Always wear protective glasses when cutting the leads of a device with clippers or a similar tool. If you do not, small bits of metal flying off the cut ends may damage your eyes.
2-2
2 Safety Precautions
2.2
2.2.1
Precautions Specific to Each Product Group
Optical semiconductor devices
When a visible semiconductor laser is operating, do not look directly into the laser beam or look through the optical system. This is highly likely to impair vision, and in the worst case may cause blindness. If it is necessary to examine the laser apparatus, for example to inspect its optical characteristics, always wear the appropriate type of laser protective glasses as stipulated by IEC standard IEC825-1.
Ensure that the current flowing in an LED device does not exceed the device's maximum rated current. This is particularly important for resin-packaged LED devices, as excessive current may cause the package resin to blow up, scattering resin fragments and causing injury. When testing the dielectric strength of a photocoupler, use testing equipment which can shut off the supply voltage to the photocoupler. If you detect a leakage current of more than 100 A, use the testing equipment to shut off the photocoupler's supply voltage; otherwise a large short-circuit current will flow continuously, and the device may break down or burst into flames, resulting in fire or injury. When incorporating a visible semiconductor laser into a design, use the device's internal photodetector or a separate photodetector to stabilize the laser's radiant power so as to ensure that laser beams exceeding the laser's rated radiant power cannot be emitted. If this stabilizing mechanism does not work and the rated radiant power is exceeded, the device may break down or the excessively powerful laser beams may cause injury.
2.2.2
Power devices
Never touch a power device while it is powered on. Also, after turning off a power device, do not touch it until it has thoroughly discharged all remaining electrical charge. Touching a power device while it is powered on or still charged could cause a severe electric shock, resulting in death or serious injury. When conducting any kind of evaluation, inspection or testing, be sure to connect the testing equipment's electrodes or probes to the device under test before powering it on. When you have finished, discharge any electrical charge remaining in the device. Connecting the electrodes or probes of testing equipment to a device while it is powered on may result in electric shock, causing injury.
2-3
2 Safety Precautions
Do not use devices under conditions which exceed their absolute maximum ratings (current, voltage, power dissipation, temperature etc.). This may cause the device to break down, causing a large short-circuit current to flow, which may in turn cause it to catch fire or explode, resulting in fire or injury. Use a unit which can detect short-circuit currents and which will shut off the power supply if a short-circuit occurs. If the power supply is not shut off, a large short-circuit current will flow continuously, which may in turn cause the device to catch fire or explode, resulting in fire or injury. When designing a case for enclosing your system, consider how best to protect the user from shrapnel in the event of the device catching fire or exploding. Flying shrapnel can cause injury. When conducting any kind of evaluation, inspection or testing, always use protective safety tools such as a cover for the device. Otherwise you may sustain injury caused by the device catching fire or exploding. Make sure that all metal casings in your design are grounded to earth. Even in modules where a device's electrodes and metal casing are insulated, capacitance in the module may cause the electrostatic potential in the casing to rise. Dielectric breakdown may cause a high voltage to be applied to the casing, causing electric shock and injury to anyone touching it. When designing the heat radiation and safety features of a system incorporating high-speed rectifiers, remember to take the device's forward and reverse losses into account. The leakage current in these devices is greater than that in ordinary rectifiers; as a result, if a high-speed rectifier is used in an extreme environment (e.g. at high temperature or high voltage), its reverse loss may increase, causing thermal runaway to occur. This may in turn cause the device to explode and scatter shrapnel, resulting in injury to the user. A design should ensure that, except when the main circuit of the device is active, reverse bias is applied to the device gate while electricity is conducted to control circuits, so that the main circuit will become inactive. Malfunction of the device may cause serious accidents or injuries.
When conducting any kind of evaluation, inspection or testing, either wear protective gloves or wait until the device has cooled properly before handling it. Devices become hot when they are operated. Even after the power has been turned off, the device will retain residual heat which may cause a burn to anyone touching it.
2.2.3
Bipolar ICs (for use in automobiles)
If your design includes an inductive load such as a motor coil, incorporate diodes or similar devices into the design to prevent negative current from flowing in. The load current generated by powering the device on and off may cause it to function erratically or to break down, which could in turn cause injury. Ensure that the power supply to any device which incorporates protective functions is stable. If the power supply is unstable, the device may operate erratically, preventing the protective functions from working correctly. If
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2 Safety Precautions
protective functions fail, the device may break down causing injury to the user.
2-5
3 General Safety Precautions and Usage Considerations
3.
General Safety Precautions and Usage Considerations
This section is designed to help you gain a better understanding of semiconductor devices, so as to ensure the safety, quality and reliability of the devices which you incorporate into your designs.
3.1
3.1.1
From Incoming to Shipping
Electrostatic discharge (ESD)
When handling individual devices (which are not yet mounted on a printed circuit board), be sure that the environment is protected against electrostatic electricity. Operators should wear anti-static clothing, and containers and other objects which come into direct contact with devices should be made of anti-static materials and should be grounded to earth via an 0.5- to 1.0-M protective resistor. Please follow the precautions described below; this is particularly important for devices which are marked "Be careful of static.". (1) Work environment
* When humidity in the working environment decreases, the human body and other insulators
can easily become charged with static electricity due to friction. Maintain the recommended humidity of 40% to 60% in the work environment, while also taking into account the fact that moisture-proof-packed products may absorb moisture after unpacking.
* Be sure that all equipment, jigs and tools in the working area are grounded to earth. * Place a conductive mat over the floor of the work area, or take other appropriate measures, so
that the floor surface is protected against static electricity and is grounded to earth. The surface resistivity should be 104 to 108 /sq and the resistance between surface and ground, 7.5 x 105 to 108 108 /sq, for a resistance between surface and ground of 7.5 x 105 to 108 ) . The purpose of this is to disperse static electricity on the surface (through resistive components) and ground it to earth. Workbench surfaces must not be constructed of low-resistance metallic materials that allow rapid static discharge when a charged device touches them directly.
* Cover the workbench surface also with a conductive mat (with a surface resistivity of 104 to
* Pay attention to the following points when using automatic equipment in your workplace:
(a) When picking up ICs with a vacuum unit, use a conductive rubber fitting on the end of the pick-up wand to protect against electrostatic charge. (b) Minimize friction on IC package surfaces. If some rubbing is unavoidable due to the device's mechanical structure, minimize the friction plane or use material with a small friction coefficient and low electrical resistance. Also, consider the use of an ionizer. (c) In sections which come into contact with device lead terminals, use a material which dissipates static electricity. (d) Ensure that no statically charged bodies (such as work clothes or the human body) touch the devices.
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3 General Safety Precautions and Usage Considerations
(e) Make sure that sections of the tape carrier which come into contact with installation devices or other electrical machinery are made of a low-resistance material. (f) Make sure that jigs and tools used in the assembly process do not touch devices.
(g) In processes in which packages may retain an electrostatic charge, use an ionizer to neutralize the ions.
* Make sure that CRT displays in the working area are protected against static charge, for
example by a VDT filter. As much as possible, avoid turning displays on and off. Doing so can cause electrostatic induction in devices.
* Keep track of charged potential in the working area by taking periodic measurements. * Ensure that work chairs are protected by an anti-static textile cover and are grounded to the
floor surface by a grounding chain. (Suggested resistance between the seat surface and grounding chain is 7.5 x 105 to 1012.) /sq; suggested resistance between surface and ground is 7.5 x 105 to 108 .)
* Install anti-static mats on storage shelf surfaces. (Suggested surface resistivity is 104 to 108 * For transport and temporary storage of devices, use containers (boxes, jigs or bags) that are
made of anti-static materials or materials which dissipate electrostatic charge.
* Make sure that cart surfaces which come into contact with device packaging are made of
materials which will conduct static electricity, and verify that they are grounded to the floor surface via a grounding chain.
* In any location where the level of static electricity is to be closely controlled, the ground
resistance level should be Class 3 or above. Use different ground wires for all items of equipment which may come into physical contact with devices.
(2) Operating environment
* Operators must wear anti-static clothing and conductive shoes
(or a leg or heel strap).
* Operators must wear a wrist strap grounded to earth via a
resistor of about 1 M.
* Soldering irons must be grounded from iron tip to earth, and must be used only at low voltages
(6 V to 24 V).
* If the tweezers you use are likely to touch the device terminals, use anti-static tweezers and in
particular avoid metallic tweezers. If a charged device touches a low-resistance tool, rapid discharge can occur. When using vacuum tweezers, attach a conductive chucking pat to the tip, and connect it to a dedicated ground used especially for anti-static purposes (suggested resistance value: 104 to 108 ). CRT).
* Do not place devices or their containers near sources of strong electrical fields (such as above a
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3 General Safety Precautions and Usage Considerations
* When storing printed circuit boards which have devices mounted on them, use a board
container or bag that is protected against static charge. To avoid the occurrence of static charge or discharge due to friction, keep the boards separate from one other and do not stack them directly on top of one another.
* Ensure, if possible, that any articles (such as clipboards) which are brought to any location
where the level of static electricity must be closely controlled are constructed of anti-static materials.
* In cases where the human body comes into direct contact with a device, be sure to wear antistatic finger covers or gloves (suggested resistance value: 108 or less).
* Equipment safety covers installed near devices should have resistance ratings of 109 or less. * If a wrist strap cannot be used for some reason, and there is a possibility of imparting friction
to devices, use an ionizer.
* The transport film used in TCP products is manufactured from materials in which static
charges tend to build up. When using these products, install an ionizer to prevent the film from being charged with static electricity. Also, ensure that no static electricity will be applied to the product's copper foils by taking measures to prevent static occuring in the peripheral equipment.
3.1.2
Vibration, impact and stress
Handle devices and packaging materials with care. To avoid damage to devices, do not toss or drop packages. Ensure that devices are not subjected to mechanical vibration or shock during transportation. Ceramic package devices and devices in canister-type packages which have empty space inside them are subject to damage from vibration and shock because the bonding wires are secured only at their ends.
Vibration
Plastic molded devices, on the other hand, have a relatively high level of resistance to vibration and mechanical shock because their bonding wires are enveloped and fixed in resin. However, when any device or package type is installed in target equipment, it is to some extent susceptible to wiring disconnections and other damage from vibration, shock and stressed solder junctions. Therefore when devices are incorporated into the design of equipment which will be subject to vibration, the structural design of the equipment must be thought out carefully. If a device is subjected to especially strong vibration, mechanical shock or stress, the package or the chip itself may crack. In products such as CCDs which incorporate window glass, this could cause surface flaws in the glass or cause the connection between the glass and the ceramic to separate. Furthermore, it is known that stress applied to a semiconductor device through the package changes the resistance characteristics of the chip because of piezoelectric effects. In analog circuit design attention must be paid to the problem of package stress as well as to the dangers of vibration and shock as described above.
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3 General Safety Precautions and Usage Considerations
3.2
3.2.1
Storage
General storage * Avoid storage locations where devices will be exposed to moisture or direct sunlight. * Follow the instructions printed on the device cartons regarding
transportation and storage.
* The storage area temperature should be kept within a
Humidity:
Temperature:
temperature range of 5C to 35C, and relative humidity should be maintained at between 45% and 75%.
* Do not store devices in the presence of harmful (especially
corrosive) gases, or in dusty conditions.
@@
* Use storage areas where there is minimal temperature fluctuation. Rapid temperature changes
can cause moisture to form on stored devices, resulting in lead oxidation or corrosion. As a result, the solderability of the leads will be degraded.
* When repacking devices, use anti-static containers. * Do not allow external forces or loads to be applied to devices while they are in storage. * If devices have been stored for more than two years, their electrical characteristics should be
tested and their leads should be tested for ease of soldering before they are used.
3.2.2
Moisture-proof packing
Moisture-proof packing should be handled with care. The handling procedure specified for each packing type should be followed scrupulously. If the proper procedures are not followed, the quality and reliability of devices may be degraded. This section describes general precautions for handling moisture-proof packing. Since the details may differ from device to device, refer also to the relevant individual datasheets or databook. (1) General precautions Follow the instructions printed on the device cartons regarding transportation and storage.
* Do not drop or toss device packing. The laminated aluminum material in it can be rendered
ineffective by rough handling.
* The storage area temperature should be kept within a temperature range of 5C to 30C, and
relative humidity should be maintained at 90% (max). Use devices within 12 months of the date marked on the package seal.
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3 General Safety Precautions and Usage Considerations
* If the 12-month storage period has expired, or if the 30% humidity indicator shown in Figure 1
is pink when the packing is opened, it may be advisable, depending on the device and packing type, to back the devices at high temperature to remove any moisture. Please refer to the table below. After the pack has been opened, use the devices in a 5C to 30C. 60% RH environment and within the effective usage period listed on the moisture-proof package. If the effective usage period has expired, or if the packing has been stored in a high-humidity environment, bake the devices at high temperature.
Packing Tray Tube Tape Moisture removal If the packing bears the "Heatproof" marking or indicates the maximum temperature which it can withstand, bake at 125C for 20 hours. (Some devices require a different procedure.) Transfer devices to trays bearing the "Heatproof" marking or indicating the temperature which they can withstand, or to aluminum tubes before baking at 125C for 20 hours. Deviced packed on tape cannot be baked and must be used within the effective usage period after unpacking, as specified on the packing.
* When baking devices, protect the devices from static electricity. * Moisture indicators can detect the approximate humidity level at a standard temperature of
25C. 6-point indicators and 3-point indicators are currently in use, but eventually all indicators will be 3-point indicators.
HUMIDITY INDICATOR 60%
50%
DANGER IF PINK CHANGE DESICCANT
40%
HUMIDITY INDICATOR
30%
40 DANGER IF PINK
20%
30
10% READ AT LAVENDER BETWEEN PINK & BLUE (a) 6-point indicator
20 READ AT LAVENDER BETWEEN PINK & BLUE (b) 3-point indicator
Figure 1 Humidity indicator
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3 General Safety Precautions and Usage Considerations
3.3
Design
Care must be exercised in the design of electronic equipment to achieve the desired reliability. It is important not only to adhere to specifications concerning absolute maximum ratings and recommended operating conditions, it is also important to consider the overall environment in which equipment will be used, including factors such as the ambient temperature, transient noise and voltage and current surges, as well as mounting conditions which affect device reliability. This section describes some general precautions which you should observe when designing circuits and when mounting devices on printed circuit boards. For more detailed information about each product family, refer to the relevant individual technical datasheets available from Toshiba.
3.3.1
Absolute maximum ratings
Do not use devices under conditions in which their absolute maximum ratings (e.g. current, voltage, power dissipation or temperature) will be exceeded. A device may break down or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user. The absolute maximum ratings are rated values which must not be exceeded during operation, even for an instant. Although absolute maximum ratings differ from product to product, they essentially concern the voltage and current at each pin, the allowable power dissipation, and the junction and storage temperatures. If the voltage or current on any pin exceeds the absolute maximum rating, the device's internal circuitry can become degraded. In the worst case, heat generated in internal circuitry can fuse wiring or cause the semiconductor chip to break down. If storage or operating temperatures exceed rated values, the package seal can deteriorate or the wires can become disconnected due to the differences between the thermal expansion coefficients of the materials from which the device is constructed.
3.3.2
Recommended operating conditions
The recommended operating conditions for each device are those necessary to guarantee that the device will operate as specified in the datasheet. If greater reliability is required, derate the device's absolute maximum ratings for voltage, current, power and temperature before using it.
3.3.3
Derating
When incorporating a device into your design, reduce its rated absolute maximum voltage, current, power dissipation and operating temperature in order to ensure high reliability. Since derating differs from application to application, refer to the technical datasheets available for the various devices used in your design.
3.3.4
Unused pins
If unused pins are left open, some devices can exhibit input instability problems, resulting in malfunctions such as abrupt increase in current flow. Similarly, if the unused output pins on a device are connected to the power supply pin, the ground pin or to other output pins, the IC may malfunction or break down. Since the details regarding the handling of unused pins differ from device to device and from pin
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3 General Safety Precautions and Usage Considerations
to pin, please follow the instructions given in the relevant individual datasheets or databook. CMOS logic IC inputs, for example, have extremely high impedance. If an input pin is left open, it can easily pick up extraneous noise and become unstable. In this case, if the input voltage level reaches an intermediate level, it is possible that both the P-channel and N-channel transistors will be turned on, allowing unwanted supply current to flow. Therefore, ensure that the unused input pins of a device are connected to the power supply (Vcc) pin or ground (GND) pin of the same device. For details of what to do with the pins of heat sinks, refer to the relevant technical datasheet and databook.
3.3.5
Latch-up
Latch-up is an abnormal condition inherent in CMOS devices, in which Vcc gets shorted to ground. This happens when a parasitic PN-PN junction (thyristor structure) internal to the CMOS chip is turned on, causing a large current of the order of several hundred mA or more to flow between Vcc and GND, eventually causing the device to break down. Latch-up occurs when the input or output voltage exceeds the rated value, causing a large current to flow in the internal chip, or when the voltage on the Vcc (Vdd) pin exceeds its rated value, forcing the internal chip into a breakdown condition. Once the chip falls into the latch-up state, even though the excess voltage may have been applied only for an instant, the large current continues to flow between Vcc (Vdd) and GND (Vss). This causes the device to heat up and, in extreme cases, to emit gas fumes as well. To avoid this problem, observe the following precautions: (1) Do not allow voltage levels on the input and output pins either to rise above Vcc (Vdd) or to fall below GND (Vss). Also, follow any prescribed power-on sequence, so that power is applied gradually or in steps rather than abruptly. (2) Do not allow any abnormal noise signals to be applied to the device. (3) Set the voltage levels of unused input pins to Vcc (Vdd) or GND (Vss). (4) Do not connect output pins to one another.
3.3.6
Input/Output protection
Wired-AND configurations, in which outputs are connected together, cannot be used, since this short-circuits the outputs. Outputs should, of course, never be connected to Vcc (Vdd) or GND (Vss). Furthermore, ICs with tri-state outputs can undergo performance degradation if a shorted output current is allowed to flow for an extended period of time. Therefore, when designing circuits, make sure that tri-state outputs will not be enabled simultaneously.
3.3.7
Load capacitance
Some devices display increased delay times if the load capacitance is large. Also, large charging and discharging currents will flow in the device, causing noise. Furthermore, since outputs are shorted for a relatively long time, wiring can become fused. Consult the technical information for the device being used to determine the recommended load capacitance.
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3 General Safety Precautions and Usage Considerations
3.3.8
Thermal design
The failure rate of semiconductor devices is greatly increased as operating temperatures increase. As shown in Figure 2, the internal thermal stress on a device is the sum of the ambient temperature and the temperature rise due to power dissipation in the device. Therefore, to achieve optimum reliability, observe the following precautions concerning thermal design: (1) Keep the ambient temperature (Ta) as low as possible. (2) If the device's dynamic power dissipation is relatively large, select the most appropriate circuit board material, and consider the use of heat sinks or of forced air cooling. Such measures will help lower the thermal resistance of the package. (3) Derate the device's absolute maximum ratings to minimize thermal stress from power dissipation. ja = jc + ca ja = (Tj-Ta) / P jc = (Tj-Tc) / P ca = (Tc-Ta) / P in which ja = thermal resistance between junction and surrounding air (C/W) jc = thermal resistance between junction and package surface, or internal thermal resistance (C/W) ca = thermal resistance between package surface and surrounding air, or external thermal resistance (C/W) Tj = junction temperature or chip temperature (C) Tc = package surface temperature or case temperature (C) Ta = ambient temperature (C) P = power dissipation (W)
Ta ca Tc jc Tj
Figure 2 Thermal resistance of package
3.3.9
Interfacing
When connecting inputs and outputs between devices, make sure input voltage (VIL/VIH) and output voltage (VOL/VOH) levels are matched. Otherwise, the devices may malfunction. When connecting devices operating at different supply voltages, such as in a dual-power-supply system, be aware that erroneous power-on and power-off sequences can result in device breakdown. For details of how to interface particular devices, consult the relevant technical datasheets and databooks. If you have any questions or doubts about interfacing, contact your nearest Toshiba office or distributor.
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3 General Safety Precautions and Usage Considerations
3.3.10
Decoupling
Spike currents generated during switching can cause Vcc (Vdd) and GND (Vss) voltage levels to fluctuate, causing ringing in the output waveform or a delay in response speed. (The power supply and GND wiring impedance is normally 50 to 100 .) For this reason, the impedance of power supply lines with respect to high frequencies must be kept low. This can be accomplished by using thick and short wiring for the Vcc (Vdd) and GND (Vss) lines and by installing decoupling capacitors (of approximately 0.01 F to 1 F capacitance) as high-frequency filters between Vcc (Vdd) and GND (Vss) at strategic locations on the printed circuit board. For low-frequency filtering, it is a good idea to install a 10- to 100-F capacitor on the printed circuit board (one capacitor will suffice). If the capacitance is excessively large, however, (e.g. several thousand F) latch-up can be a problem. Be sure to choose an appropriate capacitance value. An important point about wiring is that, in the case of high-speed logic ICs, noise is caused mainly by reflection and crosstalk, or by the power supply impedance. Reflections cause increased signal delay, ringing, overshoot and undershoot, thereby reducing the device's safety margins with respect to noise. To prevent reflections, reduce the wiring length by increasing the device mounting density so as to lower the inductance (L) and capacitance (C) in the wiring. Extreme care must be taken, however, when taking this corrective measure, since it tends to cause crosstalk between the wires. In practice, there must be a trade-off between these two factors.
3.3.11
External noise
Printed circuit boards with long I/O or signal pattern lines are vulnerable to induced noise or surges from outside sources. Consequently, malfunctions or breakdowns can result from overcurrent or overvoltage, depending on the types of device used. To protect against noise, lower the impedance of the pattern line or insert a noise-canceling circuit. Protective measures must also be taken against surges.
Input/Output Signals
For details of the appropriate protective measures for a particular device, consult the relevant databook.
3.3.12
Electromagnetic interference
Widespread use of electrical and electronic equipment in recent years has brought with it radio and TV reception problems due to electromagnetic interference. To use the radio spectrum effectively and to maintain radio communications quality, each country has formulated regulations limiting the amount of electromagnetic interference which can be generated by individual products. Electromagnetic interference includes conduction noise propagated through power supply and telephone lines, and noise from direct electromagnetic waves radiated by equipment. Different measurement methods and corrective measures are used to assess and counteract each specific type of noise. Difficulties in controlling electromagnetic interference derive from the fact that there is no method available which allows designers to calculate, at the design stage, the strength of the electromagnetic waves which will emanate from each component in a piece of equipment. For this reason, it is only after the prototype equipment has been completed that the designer can take measurements using a dedicated instrument to determine the strength of electromagnetic interference waves. Yet it is possible during system design to incorporate some measures for the
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3 General Safety Precautions and Usage Considerations
prevention of electromagnetic interference, which can facilitate taking corrective measures once the design has been completed. These include installing shields and noise filters, and increasing the thickness of the power supply wiring patterns on the printed circuit board. One effective method, for example, is to devise several shielding options during design, and then select the most suitable shielding method based on the results of measurements taken after the prototype has been completed.
3.3.13
Peripheral circuits
In most cases semiconductor devices are used with peripheral circuits and components. The input and output signal voltages and currents in these circuits must be chosen to match the semiconductor device's specifications. The following factors must be taken into account. (1) Inappropriate voltages or currents applied to a device's input pins may cause it to operate erratically. Some devices contain pull-up or pull-down resistors. When designing your system, remember to take the effect of this on the voltage and current levels into account. (2) The output pins on a device have a predetermined external circuit drive capability. If this drive capability is greater than that required, either incorporate a compensating circuit into your design or carefully select suitable components for use in external circuits.
3.3.14
Safety standards
Each country has safety standards which must be observed. These safety standards include requirements for quality assurance systems and design of device insulation. Such requirements must be fully taken into account to ensure that your design conforms to the applicable safety standards.
3.3.15
Other precautions
(1) When designing a system, be sure to incorporate fail-safe and other appropriate measures according to the intended purpose of your system. Also, be sure to debug your system under actual board-mounted conditions. (2) If a plastic-package device is placed in a strong electric field, surface leakage may occur due to the charge-up phenomenon, resulting in device malfunction. In such cases take appropriate measures to prevent this problem, for example by protecting the package surface with a conductive shield. (3) With some microcomputers and MOS memory devices, caution is required when powering on or resetting the device. To ensure that your design does not violate device specifications, consult the relevant databook for each constituent device. (4) Ensure that no conductive material or object (such as a metal pin) can drop onto and short the leads of a device mounted on a printed circuit board.
3.4
3.4.1
Inspection, Testing and Evaluation
Grounding
Ground all measuring instruments, jigs, tools and soldering irons to earth. Electrical leakage may cause a device to break down or may result in electric shock.
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3 General Safety Precautions and Usage Considerations
3.4.2
Inspection Sequence
Do not insert devices in the wrong orientation. Make sure that the positive and negative electrodes of the power supply are correctly connected. Otherwise, the rated maximum current or maximum power dissipation may be exceeded and the device may break down or undergo performance degradation, causing it to catch fire or explode, resulting in injury to the user. When conducting any kind of evaluation, inspection or testing using AC power with a peak voltage of 42.4 V or DC power exceeding 60 V, be sure to connect the electrodes or probes of the testing equipment to the device under test before powering it on. Connecting the electrodes or probes of testing equipment to a device while it is powered on may result in electric shock, causing injury. (1) Apply voltage to the test jig only after inserting the device securely into it. When applying or removing power, observe the relevant precautions, if any. (2) Make sure that the voltage applied to the device is off before removing the device from the test jig. Otherwise, the device may undergo performance degradation or be destroyed. (3) Make sure that no surge voltages from the measuring equipment are applied to the device. (4) The chips housed in tape carrier packages (TCPs) are bare chips and are therefore exposed. During inspection take care not to crack the chip or cause any flaws in it. Electrical contact may also cause a chip to become faulty. Therefore make sure that nothing comes into electrical contact with the chip.
3.5
Mounting
There are essentially two main types of semiconductor device package: lead insertion and surface mount. During mounting on printed circuit boards, devices can become contaminated by flux or damaged by thermal stress from the soldering process. With surface-mount devices in particular, the most significant problem is thermal stress from solder reflow, when the entire package is subjected to heat. This section describes a recommended temperature profile for each mounting method, as well as general precautions which you should take when mounting devices on printed circuit boards. Note, however, that even for devices with the same package type, the appropriate mounting method varies according to the size of the chip and the size and shape of the lead frame. Therefore, please consult the relevant technical datasheet and databook.
3.5.1
Lead forming
Always wear protective glasses when cutting the leads of a device with clippers or a similar tool. If you do not, small bits of metal flying off the cut ends may damage your eyes. Do not touch the tips of device leads. Because some types of device have leads with pointed tips, you may prick your finger. Semiconductor devices must undergo a process in which the leads are cut and formed before the devices can be mounted on a printed circuit board. If undue stress is applied to the interior of a device during this process, mechanical breakdown or performance degradation can result. This is attributable primarily to differences between the stress on the device's external leads and the stress on the internal leads. If the relative difference is great enough, the device's internal leads, adhesive properties or sealant can be damaged. Observe these precautions during the leadforming process (this does not apply to surface-mount devices):
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3 General Safety Precautions and Usage Considerations
(1) Lead insertion hole intervals on the printed circuit board should match the lead pitch of the device precisely. (2) If lead insertion hole intervals on the printed circuit board do not precisely match the lead pitch of the device, do not attempt to forcibly insert devices by pressing on them or by pulling on their leads. (3) For the minimum clearance specification between a device and a printed circuit board, refer to the relevant device's datasheet and databook. If necessary, achieve the required clearance by forming the device's leads appropriately. Do not use the spacers which are used to raise devices above the surface of the printed circuit board during soldering to achieve clearance. These spacers normally continue to expand due to heat, even after the solder has begun to solidify; this applies severe stress to the device. (4) Observe the following precautions when forming the leads of a device prior to mounting.
* Use a tool or jig to secure the lead at its base (where the lead meets the device package) while
bending so as to avoid mechanical stress to the device. Also avoid bending or stretching device leads repeatedly.
* Be careful not to damage the lead during lead forming. * Follow any other precautions described in the individual datasheets and databooks for each
device and package type.
3.5.2
Socket mounting
(1) When socket mounting devices on a printed circuit board, use sockets which match the inserted device's package. (2) Use sockets whose contacts have the appropriate contact pressure. If the contact pressure is insufficient, the socket may not make a perfect contact when the device is repeatedly inserted and removed; if the pressure is excessively high, the device leads may be bent or damaged when they are inserted into or removed from the socket. (3) When soldering sockets to the printed circuit board, use sockets whose construction prevents flux from penetrating into the contacts or which allows flux to be completely cleaned off. (4) Make sure the coating agent applied to the printed circuit board for moisture-proofing purposes does not stick to the socket contacts. (5) If the device leads are severely bent by a socket as it is inserted or removed and you wish to repair the leads so as to continue using the device, make sure that this lead correction is only performed once. Do not use devices whose leads have been corrected more than once. (6) If the printed circuit board with the devices mounted on it will be subjected to vibration from external sources, use sockets which have a strong contact pressure so as to prevent the sockets and devices from vibrating relative to one another.
3.5.3
Soldering temperature profile
The soldering temperature and heating time vary from device to device. Therefore, when specifying the mounting conditions, refer to the individual datasheets and databooks for the devices used.
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3 General Safety Precautions and Usage Considerations
(1) Using a soldering iron Complete soldering within ten seconds for lead temperatures of up to 260C, or within three seconds for lead temperatures of up to 350C. (2) Using medium infrared ray reflow
* Heating top and bottom with long or medium infrared rays is recommended (see Figure 3).
Medium infrared ray heater (reflow) Product flow
Long infrared ray heater (preheating)
Figure 3 Heating top and bottom with long or medium infrared rays
* Complete the infrared ray reflow process within 30 seconds at a package surface temperature
of between 210C and 240C.
* Refer to Figure 4 for an example of a good temperature profile for infrared or hot air reflow.
(C) 240 Package surface temperature
210
160 140 60-120 s 30 s or less Time (s)
Figure 4 Sample temperature profile for infrared or hot air reflow (3) Using hot air reflow
* Complete hot air reflow within 30 seconds at a package surface temperature of between 210C
and 240C.
* For an example of a recommended temperature profile, refer to Figure 4 above.
(4) Using solder flow
* Apply preheating for 60 to 120 seconds at a temperature of 150C. * For lead insertion-type packages, complete solder flow within 10 seconds with the
temperature at the stopper (or, if there is no stopper, at a location more than 1.5 mm from the body) which does not exceed 260C.
* For surface-mount packages, complete soldering within 5 seconds at a temperature of 250C or
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3 General Safety Precautions and Usage Considerations
less in order to prevent thermal stress in the device.
* Figure 5 shows an example of a recommended temperature profile for surface-mount packages
using solder flow.
(C) 250 Package surface temperature
160 140 60-120 s 5s or less
Time (s)
Figure 5 Sample temperature profile for solder flow
3.5.4
Flux cleaning and ultrasonic cleaning
(1) When cleaning circuit boards to remove flux, make sure that no residual reactive ions such as Na or Cl remain. Note that organic solvents react with water to generate hydrogen chloride and other corrosive gases which can degrade device performance. (2) Washing devices with water will not cause any problems. However, make sure that no reactive ions such as sodium and chlorine are left as a residue. Also, be sure to dry devices sufficiently after washing. (3) Do not rub device markings with a brush or with your hand during cleaning or while the devices are still wet from the cleaning agent. Doing so can rub off the markings. (4) The dip cleaning, shower cleaning and steam cleaning processes all involve the chemical action of a solvent. Use only recommended solvents for these cleaning methods. When immersing devices in a solvent or steam bath, make sure that the temperature of the liquid is 50C or below, and that the circuit board is removed from the bath within one minute. (5) Ultrasonic cleaning should not be used with hermetically-sealed ceramic packages such as a leadless chip carrier (LCC), pin grid array (PGA) or charge-coupled device (CCD), because the bonding wires can become disconnected due to resonance during the cleaning process. Even if a device package allows ultrasonic cleaning, limit the duration of ultrasonic cleaning to as short a time as possible, since long hours of ultrasonic cleaning degrade the adhesion between the mold resin and the frame material. The following ultrasonic cleaning conditions are recommended: Frequency: 27 kHz 29 kHz Ultrasonic output power: 300 W or less (0.25 W/cm2 or less) Cleaning time: 30 seconds or less Suspend the circuit board in the solvent bath during ultrasonic cleaning in such a way that the ultrasonic vibrator does not come into direct contact with the circuit board or the device.
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3 General Safety Precautions and Usage Considerations
3.5.5
No cleaning
If analog devices or high-speed devices are used without being cleaned, flux residues may cause minute amounts of leakage between pins. Similarly, dew condensation, which occurs in environments containing residual chlorine when power to the device is on, may cause betweenlead leakage or migration. Therefore, Toshiba recommends that these devices be cleaned. However, if the flux used contains only a small amount of halogen (0.05W% or less), the devices may be used without cleaning without any problems.
3.5.6
Mounting tape carrier packages (TCPs)
(1) When tape carrier packages (TCPs) are mounted, measures must be taken to prevent electrostatic breakdown of the devices. (2) If devices are being picked up from tape, or outer lead bonding (OLB) mounting is being carried out, consult the manufacturer of the insertion machine which is being used, in order to establish the optimum mounting conditions in advance and to avoid any possible hazards. (3) The base film, which is made of polyimide, is hard and thin. Be careful not to cut or scratch your hands or any objects while handling the tape. (4) When punching tape, try not to scatter broken pieces of tape too much. (5) Treat the extra film, reels and spacers left after punching as industrial waste, taking care not to destroy or pollute the environment. (6) Chips housed in tape carrier packages (TCPs) are bare chips and therefore have their reverse side exposed. To ensure that the chip will not be cracked during mounting, ensure that no mechanical shock is applied to the reverse side of the chip. Electrical contact may also cause a chip to fail. Therefore, when mounting devices, make sure that nothing comes into electrical contact with the reverse side of the chip. If your design requires connecting the reverse side of the chip to the circuit board, please consult Toshiba or a Toshiba distributor beforehand.
3.5.7
Mounting chips
Devices delivered in chip form tend to degrade or break under external forces much more easily than plastic-packaged devices. Therefore, caution is required when handling this type of device. (1) Mount devices in a properly prepared environment so that chip surfaces will not be exposed to polluted ambient air or other polluted substances. (2) When handling chips, be careful not to expose them to static electricity. In particular, measures must be taken to prevent static damage during the mounting of chips. With this in mind, Toshiba recommend mounting all peripheral parts first and then mounting chips last (after all other components have been mounted). (3) Make sure that PCBs (or any other kind of circuit board) on which chips are being mounted do not have any chemical residues on them (such as the chemicals which were used for etching the PCBs). (4) When mounting chips on a board, use the method of assembly that is most suitable for maintaining the appropriate electrical, thermal and mechanical properties of the semiconductor devices used. * For details of devices in chip form, refer to the relevant device's individual datasheets.
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3 General Safety Precautions and Usage Considerations
3.5.8
Circuit board coating
When devices are to be used in equipment requiring a high degree of reliability or in extreme environments (where moisture, corrosive gas or dust is present), circuit boards may be coated for protection. However, before doing so, you must carefully consider the possible stress and contamination effects that may result and then choose the coating resin which results in the minimum level of stress to the device.
3.5.9
Heat sinks
(1) When attaching a heat sink to a device, be careful not to apply excessive force to the device in the process. (2) When attaching a device to a heat sink by fixing it at two or more locations, evenly tighten all the screws in stages (i.e. do not fully tighten one screw while the rest are still only loosely tightened). Finally, fully tighten all the screws up to the specified torque. (3) Drill holes for screws in the heat sink exactly as specified. Smooth the surface by removing burrs and protrusions or indentations which might interfere with the installation of any part of the device. (4) A coating of silicone compound can be applied between the heat sink and the device to improve heat conductivity. Be sure to apply the coating thinly and evenly; do not use too much. Also, be sure to use a non-volatile compound, as volatile compounds can crack after a time, causing the heat radiation properties of the heat sink to deteriorate. (5) If the device is housed in a plastic package, use caution when selecting the type of silicone compound to be applied between the heat sink and the device. With some types, the base oil separates and penetrates the plastic package, significantly reducing the useful life of the device. Two recommended silicone compounds in which base oil separation is not a problem are YG6260 from Toshiba Silicone. (6) Heat-sink-equipped devices can become very hot during operation. Do not touch them, or you may sustain a burn.
3.5.10
Tightening torque
(1) Make sure the screws are tightened with fastening torques not exceeding the torque values stipulated in individual datasheets and databooks for the devices used. (2) Do not allow a power screwdriver (electrical or air-driven) to touch devices.
3.5.11
Repeated device mounting and usage
Do not remount or re-use devices which fall into the categories listed below; these devices may cause significant problems relating to performance and reliability. (1) Devices which have been removed from the board after soldering (2) Devices which have been inserted in the wrong orientation or which have had reverse current applied (3) Devices which have undergone lead forming more than once
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3 General Safety Precautions and Usage Considerations
3.6
3.6.1
Protecting Devices in the Field
Temperature
Semiconductor devices are generally more sensitive to temperature than are other electronic components. The various electrical characteristics of a semiconductor device are dependent on the ambient temperature at which the device is used. It is therefore necessary to understand the temperature characteristics of a device and to incorporate device derating into circuit design. Note also that if a device is used above its maximum temperature rating, device deterioration is more rapid and it will reach the end of its usable life sooner than expected.
3.6.2
Humidity
Resin-molded devices are sometimes improperly sealed. When these devices are used for an extended period of time in a high-humidity environment, moisture can penetrate into the device and cause chip degradation or malfunction. Furthermore, when devices are mounted on a regular printed circuit board, the impedance between wiring components can decrease under highhumidity conditions. In systems which require a high signal-source impedance, circuit board leakage or leakage between device lead pins can cause malfunctions. The application of a moisture-proof treatment to the device surface should be considered in this case. On the other hand, operation under low-humidity conditions can damage a device due to the occurrence of electrostatic discharge. Unless damp-proofing measures have been specifically taken, use devices only in environments with appropriate ambient moisture levels (i.e. within a relative humidity range of 40% to 60%).
3.6.3
Corrosive gases
Corrosive gases can cause chemical reactions in devices, degrading device characteristics. For example, sulphur-bearing corrosive gases emanating from rubber placed near a device (accompanied by condensation under high-humidity conditions) can corrode a device's leads. The resulting chemical reaction between leads forms foreign particles which can cause electrical leakage.
3.6.4
Radioactive and cosmic rays
Most industrial and consumer semiconductor devices are not designed with protection against radioactive and cosmic rays. Devices used in aerospace equipment or in radioactive environments must therefore be shielded.
3.6.5
Strong electrical and magnetic fields
Devices exposed to strong magnetic fields can undergo a polarization phenomenon in their plastic material, or within the chip, which gives rise to abnormal symptoms such as impedance changes or increased leakage current. Failures have been reported in LSIs mounted near malfunctioning deflection yokes in TV sets. In such cases the device's installation location must be changed or the device must be shielded against the electrical or magnetic field. Shielding against magnetism is especially necessary for devices used in an alternating magnetic field because of the electromotive forces generated in this type of environment.
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3 General Safety Precautions and Usage Considerations
3.6.6
Interference from light (ultraviolet rays, sunlight, fluorescent lamps and incandescent lamps)
Light striking a semiconductor device generates electromotive force due to photoelectric effects. In some cases the device can malfunction. This is especially true for devices in which the internal chip is exposed. When designing circuits, make sure that devices are protected against incident light from external sources. This problem is not limited to optical semiconductors and EPROMs. All types of device can be affected by light.
3.6.7
Dust and oil
Just like corrosive gases, dust and oil can cause chemical reactions in devices, which will adversely affect a device's electrical characteristics. To avoid this problem, do not use devices in dusty or oily environments. This is especially important for optical devices because dust and oil can affect a device's optical characteristics as well as its physical integrity and the electrical performance factors mentioned above.
3.6.8
Fire
Semiconductor devices are combustible; they can emit smoke and catch fire if heated sufficiently. When this happens, some devices may generate poisonous gases. Devices should therefore never be used in close proximity to an open flame or a heat-generating body, or near flammable or combustible materials.
3.7
Disposal of Devices and Packing Materials
When discarding unused devices and packing materials, follow all procedures specified by local regulations in order to protect the environment against contamination.
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4 Precautions and Usage Considerations
4.
Precautions and Usage Considerations
This section describes matters specific to each product group which need to be taken into consideration when using devices. If the same item is described in Sections 3 and 4, the description in Section 4 takes precedence.
4.1
4.1.1
Microcontrollers
Design
(1) Using resonators which are not specifically recommended for use Resonators recommended for use with Toshiba products in microcontroller oscillator applications are listed in Toshiba databooks along with information about oscillation conditions. If you use a resonator not included in this list, please consult Toshiba or the resonator manufacturer concerning the suitability of the device for your application. (2) Undefined functions In some microcontrollers certain instruction code values do not constitute valid processor instructions. Also, it is possible that the values of bits in registers will become undefined. Take care in your applications not to use invalid instructions or to let register bit values become undefined.
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4 Precautions and Usage Considerations
4-2
TX3916F
Chapter 1 The TMPR3916
1.
1.1
The TMPR3916
Applications and References
The TMPR3916 is a family member of Toshiba's 32-bit system RISC family. As an application-specific standard product (ASSP) it is designed for a wide range of applications such as: * * * * * Car Navigation Systems Driver Information Displays Personal Digital Assistants (PDAs) Musical Instruments Electronic Book Players
The TMPR3916 uses a TX39/H core as its CPU. The TX39/H CPU core is a RISC processor developed by Toshiba based on the R3000A architecture of MIPS Technologies Inc. . In addition to the processor core, this ASSP includes peripheral circuits such as a graphics display controller, a memory controller, a DMA controller, several serial communication interfaces, CAN-bus interfaces, interval timers and general purpose I/Os. Please refer to the following document for information about the TX39 core architecture, including the instruction set: 32-Bit TX System RISC TX39 Family Architecture (Document Number 44137D)
1-1
Preliminary
Chapter 1 The TMPR3916
1.2
Features
Miscellaneous: * * * * * * * * 60 MHz maximum operating frequency: 208 pin QFP package (QFP208-P-2828-0.50) 3.3 V power supply voltage ca. 1200mW Maximum Power Dissipation -40C to 85C operating ambient temperature Built-in clock generator 5V tolerant I/Os on UARTs, TXSEI and CAN-bus interface Unified memory architecture with a high performance dual bus structure (Video bus + CPU bus)
Graphics Display Controller: * * * * * * * * * * Four-layer (A-D) overlay hardware processing with transparent color: Layer A, B can display 256 out of 64 K colors each Layer C, D can display 16 out of 64 K colors each Alternatively layer A may be configured in picture mode with 64K colors SDRAM and SRAM frame-buffer memory (SRAM recommended only for low resolutions) Burst access to frame-buffer memory 16 bytes built-in dot buffer Built-in color look-up tables (for plane A-D, 544 colors in total) Built-in three-channel 6-bit video DAC, alternatively connection to digital displays (digital RGB output) Dotclock, horizontal and vertical synchronisation signals can be generated internally or input from external device
Built-in TX39 Core: * * * * Toshiba-developed TX39H core based on MIPS R3000A architecture 4 KB Instruction Cache, 1 KB Data Cache Built-in debug support unit for in-system debugging incl. real time PC-tracing Big-endian coding
Peripheral Controllers: * * * * * * * Memory Controller (MEMC), 4 channels for SRAM, ROM, Flash SDRAM controller (SDRAMC), 2 channels DMA controller (DMAC), 2 channels Interrupt controller (INTC), 13 internal interrupts, 3 external interrupts, 1 non-maskable interrupt (NMI) Serial I/O : UART 4 channels, TXSEI 1 channel (SPI compatible, with FIFOs) CAN-bus controller (TXCAN), 2 channels, 16 mailboxes each 30 Pin General Purpose I/Os (PORT)
1-2
Preliminary
Chapter 1 The TMPR3916
1.3
Differences Between TX3903AF and TMPR3916
In catchwords this section explains changed features of TMPR3916 in comparison to its predecessor TX3903AF. For detailed information please have a deeper look into this document. * * * * * * * * * * * * * 60 MHz operating frequency added dual CAN device added TXSEI functionality added two channel SDRAM Controller separate Video- and CPU-bus to SDRAM in order to increase system performance removed EDO-DRAM channels from MEMC no more support of pipelined burst SRAM graphics display controller: increased number of colors from 16 to 256 in layer A and B raised number of 16 general purpose IOs to 30 and added capability of triggering interrupt extended timer functionality to PWM-support increased number of internal interrupts modified UART incl. register structure external bus-master functionality is not supported any more
1-3
Preliminary
Chapter 1 The TMPR3916
1.4
Structure of TMPR3916 and a System Example
The following picture shows the block diagram of the TMPR3916:
XTAL1,PLLOFF, CLKEN XTAL2
SYSCLK
Clock Generator / PLL
TX39/H Core
pcst[2:0] dclk dsa0/tpc dbge sdi/dint dreset test[2:0]
RESET HALT
4KB I$ DSU CORE 1KB D$
SEI TIMER SCI
Channel Channel Channel Channel 0 1 2 3
EXT[2:0] NMI
INTC
TXCAN CPU bus
RXCAN0, RXCAN1 TXCAN0, TXCAN1
PIO
PIO[29:16] / SCI, SEI PIO[15:0] / Digital RGB
Channel 0 Channel 1
HSYNC
GDC DMAC Channel 0 Channel 1 video bus VIEWDAC
VSYNC/CSYNC HDISP DOTCLK
DREQ0 DACK0
ROUT GOUT BOUT
Memory Controller (MC)
RAS CAS WE CKE CS[5:2] CS[1:0]
MEMC
SDRAMC
RD, WR, LAST
BSTART, BURST
ACK, BUSERR
Figure 1.4.1 Block Diagram TMPR3916
BE[3:0]
D[31:0]
A[26:2]
1-4
Preliminary
Chapter 1 The TMPR3916
The following picture shows a system example with TMPR3916:
GDC
HSYNC VSYNC
LC Display
RGB
TMPR3916
SIO SEI CAN
GPS
I/O Ctrl
Gyro
SDRAM MC
ROM
CDROM I/F
SRAM
Figure 1.4.2 System Example Using TMPR3916
1-5
Preliminary
Chapter 1 The TMPR3916
1.5
Address Map
The following table shows the memory map of TMPR3916.
Memory Area of TX39-CPU Kernel Uncached/ Cached (kseg0, kseg1) Physical Address 0x0000 0000 SDRAM, SRAM, ROM * 0x1C00 0000 interrupt vector at 0x0000 0080 devices of TMPR3916 Memory Device Special Use in TMPR3916
internal register SDRAM, SRAM, ROM * Boot ROM
0x1E00 0000
0x1FC0 0000
start address after reset or NMI
Inaccessible
0x2000 0000
0x4000 0000 User / Kernel Cached (kuseg)
SDRAM, SRAM, ROM *
User / Kernel Uncached (kuseg - reserved) Kernel Cached (kseg2) Kernel Uncached (kseg2 - reserved)
0xBF00 0000
0xC000 0000
0xFF00 0000
Figure 1.5.1 TMPR3916's Memory Map For SDRAM, SRAM or ROM shown in the above table, the software can define the address range of the connected memory devices. For further information see chapter "Memory Controller".
*
1-6
Preliminary
Chapter 1 The TMPR3916
The following table shows the address ranges of the internal devices: Address Range (physical address)
0x1C00_0000 .. 0x1C00_07FF 0x1C00_8000 .. 0x1C00_FFFF 0x1C01_0000 .. 0x1C01_FFFF 0x1C02_0000 .. 0x1C02_7FFF 0x1C02_8000 .. 0x1C02_FFFF 0x1C03_0000 .. 0x1C03_FFFF 0x1C04_0000 .. 0x1C04_FFFF 0x1C05_0000 .. 0x1C05_FFFF 0x1C06_0000 .. 0x1C06_FFFF 0x1C07_0000 .. 0x1C07_7FFF 0x1C07_8000 .. 0x1C07_FFFF 0x1C08_0000 .. 0x1C08_FFFF
Address Range (virtual address)
0xBC00_0000 .. 0xBC00_07FF 0xBC00_8000 .. 0xBC00_FFFF 0xBC01_0000 .. 0xBC01_FFFF 0xBC02_0000 .. 0xBC02_7FFF 0xBC02_8000 .. 0xBC02_FFFF 0xBC03_0000 .. 0xBC03_FFFF 0xBC04_0000 .. 0xBC04_FFFF 0xBC05_0000 .. 0xBC05_FFFF 0xBC06_0000 .. 0xBC06_FFFF 0xBC07_0000 .. 0xBC07_7FFF 0xBC07_8000 .. 0xBC07_FFFF 0xBC08_0000 .. 0xBC08_FFFF
Device
Asynchronous Serial Interface (UART)
Synchronous Serial Interface (TXSEI)
TIMER
Memory Controller (MEMC)
Memory Controller (SDRAMC)
Parallel Interface (PORT)
Interrupt Controller (INTC)
Graphic Display Controller (GDC)
Direct Memory Access Controller (DMAC)
CAN Module (TXCAN), channel 0
CAN Module (TXCAN), channel 1
Chip Configuration Register (CCR)
Figure 1.5.2 Physical and Virtual Addresses for Internal Devices Note: Please note that addresses seen on GBUS are physical. Therefore virtual addresses can only be used in program code and will be translated before being output to the bus.
1-7
Preliminary
Chapter 1 The TMPR3916
1.6
Clocks
The TMPR3916 incorporates an eight-times PLL clock generator. Connect a crystal oscillator with 1/8 the frequency of the processor clock (processor clock = TX39 core input clock frequency). To reduce power dissipation and simplify system design, the TMPR3916 can control the TX39 core operating frequency and the bus operation reference frequency. Clock Types: * Master clock Master clock regulates the TMPR3916 operations. The clock is eight times the frequency of the external crystal oscillator. * Processor clock This clock is used for TMPR3916 processor core operations. It has the same frequency as the master clock. (When using this clock, set reduced frequency indicator RF[1:0] of the core configuration register to 00. The processor clock will not operate if RF is set to any other value.) * System clock The system clock regulates the TMPR3916 bus operations. It is generated from the processor clock and is of the same frequency and phase. This clock is output to pin SYSCLK. Setting the CLKEN pin to low stops all clocks of the device. The SYSCLK pin is set to high in this state and power-consumption is reduced to a minimum. The processor can resume its function immediately after the CLKEN pin has been asserted. For further information see chapter "Electrical Characteristics".
1-8
Preliminary
Chapter 1 The TMPR3916
1.7
Resets
Setting RESET* = Low resets the TMPR3916. RESET* should be held Low for at least 10 cycles of system clock (SYSCLK). Because the RESET* signal is synchronized with the TMPR3916 internal clock, the RESET* signal can be set asynchronously to system clock. At a reset the TMPR3916 will do the following operations: * * Pipeline will be stalled, internal states reset. The valid and lock bits of the TX39 cache will be cleared. During reset period the output signals have the following states: A[31:2] D[31:0] BE[3:0]* = = = undefined undefined "High" "High" "High" "High" continues outputting clock
RD*, WR* = BURST* LAST* SYSCLK = = =
1-9
Preliminary
Chapter 1 The TMPR3916
1.8
Time-Out-Error Control Unit
This unit is a kind of watchdog unit for the internal CPU-bus. When a master sends a GBSTART signal, the Time-Out Error Control Unit starts counting cycles. If no reaction has been detected on the bus, an internal acknowledging GACK is generated after 1024 cycles so that the bus is free for interaction again.
1.9
Operating Modes of TMPR3916
In Normal Mode, the TX39 core and peripheral circuits operate at maximum frequency. Halt Mode halts the core operations and reduces power dissipation by stopping the clock in the TX39 core. To switch to Halt mode, set the Halt bit of the Configuration Register in TX39 core. In Halt mode, the TX39 core holds the status of the pipeline processing and stops the core operations. The write buffer does not stop. If data remains in the write buffer when Halt mode is selected, write operations continue until the write buffer becomes empty. Also SYSCLK does not stop. The processor is released from HALT mode by using the NMI* signal, RESET* signal or by any kind of enabled interrupt. The corresponding exception handler is executed after the HALT mode has been released. Doze Mode halts some TX39 core operations and reduces power dissipation. Unlike Halt mode, only some clocks in the processor core stop, allowing external bus release requests to be received. Also the peripheral blocks continue operating normally in Doze mode. To switch to Doze mode, set the Doze bit of the configuration register in TX39 core. Standby Mode halts the clock generator PLL circuit operation and reduces power dissipation. First, set CLKEN pin to low to stop the clock supply. Then, set PLLOFF* pin to low to halt the PLL circuit operations.
1-10
Preliminary
Chapter 1 The TMPR3916
1.10 Chip Configuration Register (CCR)
The configuration register is used to configure chip functions concerning more than one module.
Bit Name Bit Name Bit Name Bit Name 7 15 23 14 6 DMA1CC 5 13 22 21 CANM 12 SEIMUX 4 3 11 2 DMA0CC 10 31 30 29 20 19 18 28 27 26 25 VIEWDAC 17 CANDIV 9 TOE 1 8 BEOW 0 24 SFB 16
Bit
31:26 25
Name
VIEWDAC Wired to zero
Function
Reset Value
0 1
R/W
R R/W
By using this bit it is possible to power down the VIEWDAC. 1 = Enables the VIEWDAC (default) 0 = Disables the VIEWDAC SRAM Frame Buffer: 0 = Display frame is stored in SDRAM 1 = Display frame is stored in SRAM Wired to zero CAN operation mode 00 = Normal mode X1 = Internal test mode 10 = 2 internal CAN on one TX/RX pair, 1 Transceiver Wired to zero The CANDIV bits set the clock divider for the CAN modules. The following table shows possible settings and the corresponding divider ratios. 000 = Invalid setting 001 = System clock divided by 2 010 = System clock divided by 3 (default) 011 = System clock divided by 4 100 = System clock divided by 5 101 = System clock divided by 6 110 = System clock divided by 7 111 = System clock divided by 8 Wired to zero Determines whether the TXSEI or the UART use pins PIO16 to PIO29. 0 = The UART uses pins 1 = The TXSEI uses pins Wired to zero Time-Out Error Control The time-out error counter aborts bus transactions with exception after 1024 cycles, if they are not responded to. 0 = No time-out on internal bus 1 = Abort not responded access on internal bus
24
SFB
0
R/W
23:22 21:20
CANM
00 00
R R/W
19 18:16
CANDIV
0 010
R R/W
15:13 12
SEIMUX
0 1
R R/W
11:10 9
TOE
0 1
R R/W
1-11
Preliminary
Chapter 1 The TMPR3916
Reset Value
1
Bit
8
Name
BEOW
Function
Bus Error on Write This bit determines, if a write transaction on internal bus will aborted, when no device responds after 1024 cycles. 0 = No bus-error on time-out at write 1 = Generate bus-error on time-out at write These bits are used to select devices for DMA transfers of DMA channel 1. 0000 = UART0, Transmission 0001 = UART0, Reception 0010 = UART1, Transmission 0011 = UART1, Reception 0100 = UART2, Transmission 0101 = UART2, Reception 0110 = UART3, Transmission 0111 = UART3, Reception 1000 = TXSEI, Transmission 1001 = TXSEI, Reception 1010 = External Device 1111 = No device selected (reset value) Other settings are invalid These bits are used to select devices for DMA transfers of DMA channel 0. The settings are similar to DMA1CC.
R/W
R/W
7:4
DMA1CC
1111
R/W
3:0
DMA0CC
1111
R/W
1-12
Preliminary
Chapter 2 Memory Controller (MC)
2.
Memory Controller (MC)
This system's memory controller consists of two modules: the SDRAM Controller (SDRAMC) and MEMC for other types of memory. Six multi-purpose memory channels can be administrated: While the channels 0 and 1 are assigned to the SDRAM controller, the memory controller's channels are numbered from 2 to 5. The SDRAM Controller contains the following features: * * * * * * * * * * * * * * * uses memory architecture single-data-rate SDRAM 2 memory channels with 32 bit width, 16 bit width connectivity is not supported for SDRAM devices base address, mask, DRAM size & organization configurable for each channel (same physical address space on both Video and System-Busses) true dual G-Bus connectivity read bursts 4, 8, 16, 32 words, single read accesses, single write accesses different, mixed burst sizes on both busses are possible fair memory arbitration, predictable latency memory arbitrated on a first come first serve basis for the case of a simultaneous transaction request, the prioritized G-Bus can be configured one word write-back buffer to reduce bus utilization during write operations low-power / self-refresh mode supported background refresh during MEMC accesses built-in power-up logic programmable refresh cycle
The MEMC contains the following features: * * * * * * * * 4 separate channels Support for ROM, MASK ROM, PAGE MODE ROM, EPROM, EEPROM, SRAM, and FLASH devices Support for Page-Mode Base Address and size programmable per channel external Acknowledge mode for external ASIC slave device connectivity Data Bus width of 16-bit/32-bit is selectable by channel Supports programmable Setup and Hold Time for Address, Chip Enable, Write Enable Signals Channel 5 supports BOOT options
2-1
Preliminary
Chapter 2 Memory Controller (MC)
2.1
Structure of Memory Controller
TMPR3916 owns two internal busses, the system bus and the video bus. The system bus can be accessed by the TX39 core and other devices capable of being master on the bus. Additionally, the TMPR3916 provides a second, so called video bus. The video bus is used by the GDC in order to read picture data from the SDRAM frame buffer. The GDC is the only device on that bus and is not able to write data into SDRAM. It is only possible to write data into the frame buffer via the system bus. Due to system performance considerations it is recommended to use SDRAM memory for frame buffer, though it is also possible to locate the frame buffer in memory devices accessible by the MEMC. For this purpose the TMPR3916 provides a bridge between system and video bus. In order to activate this bridge the SFB bit in Chip Configuration Register (CCR) needs to be asserted. It has to be assured that the GDC is not accessing SDRAM mapped memory in this case. In this mode, the system-performance is restricted by the higher utilization of the system bus and the reduced throughput to the frame buffer memory devices. The following figure shows the structure of the memory controller:
internal system-bus MEMC Registered Interface interface to devices connected to the TMPR3916
Video to System Bus Bridge SDRAM Controller internal video-bus
Figure 2.1.1 Data Flow in Memory Controller
2-2
Preliminary
Chapter 2 Memory Controller (MC)
2.2
Example Memory Configuration
The following figures show examples how to connect different devices to the TMPR3916. It is possible to have a mixture of different kinds of memories because timing & device configurations are programmable for each channel in the MC. Keep in mind that additionally a boot device must always be connected to channel 5 of the memory controller! Asynchronous SRAM connected to the TMPR3916 (16 bit data width):
CS[x]* A[15:2] WR* RD* BE[3]* BE[2]* BE[1]* BE[0]* D[15:0] D[31:16]
CE* A WE* OE* LB* UB* D[15:0]
Figure 2.2.1 16-Bit Asynchronous SRAM Connected to TMPR3916
TMPR3916
Async. SRAM
2-3
Preliminary
Chapter 2 Memory Controller (MC)
Two asynchronous SRAMs connected to one channel of the TMPR3916 :
CS[x] A WR* RD* BE[3]* BE[2]* BE[1]* BE[0]*
CE* A WE* OE* LB* UB* D[15:0]
TMPR3916
D[31:16] CE* A WE* OE* LB* UB* D[15:0] D[15:0]
Figure 2.2.2 2 x 16-Bit Asynchronous SRAM Connected to One 32-Bit Memory Channel
Connection of an external slave device with a data width of 16 bit :
SYSCLK CS[x]* A[15:2] BSTART* LAST* BURST* WR* ACK BUSERR*
SYSCLK CS* A
RW* ACK* BUSERR*
BE[1:0]* D[15:0]
BE[1:0] D[15:0]
Figure 2.2.3 16-Bit External Slave Device Connected to Memory Channel
External Slave
Preliminary
TMPR3916
BSTART* LAST* BURST*
2-4
Async. SRAM
Async. SRAM
Chapter 2 Memory Controller (MC)
Connection of an external slave device with a data width of 32 bit :
SYSCLK CS[x*] A[26:2] BSTART* LAST* BURST* RD* ACK* BUSERR*
SYSCLK CS* A BSTART* LAST* BURST* RW* ACKOUT* BUSERROUT*
BE[3:0]* D[31:0]
BE[3:0]* D[31:0]
Figure 2.2.4 32-Bit External Slave Device Connected to Memory Channel The following figure shows the connection of a 32 bit width 16Mbit SDRAM device to the TMPR3916. As can be seen on the chip select signal connectivity (CS0) the device is accessed via channel 0 of the SDRAM Controller.
SYSCLK CKE CS0* A[12:2] A[16:15]
CLK CKE CS* A[10:0] BA[1:0] RAS* CAS* WE*
TMPR3916
BE[3:0]* D[31:0]
DQM DQ[31:0]
Figure 2.2.5 16 Mbit x 32 SDRAM Device Connected to Memory Channel
SDRAM 16MBit*32
Preliminary
RAS* CAS* WE*
2-5
External Slave
TMPR3916
Chapter 2 Memory Controller (MC)
2.3
Ports of Memory Controller
The SDRAM controller externally connects up to two channels of SDRAM memory. Each of the two SDRAM controller channels has its own organization register and can support different device sizes and organization. The timing settings are shared for both channels and must be the same for both channels. Refresh is conducted on both channels in parallel. The memory channels share the memory data, address and control busses with the exception of the chipselect signal, which is wired individually for each channel. Each channel must be connected with a width of 32 bits. Devices with organizations of 4, 8, 16 and 32 bit width can be used as long as the connected devices jointly form a 32 bit channel. The following table summarizes the externally connected memory signals. Signal
SYSCLK A[14:2] A[16:15] RAS* CAS* WE* CKE CS*[1:0]
Type
OUT OUT OUT OUT OUT OUT OUT OUT DRAM Clock
Description
Row/Column Address Bus, connect to A at the SDRAM device Bank Address Bus, connect to BA at the SDRAM device Row Access Strobe signal Column Access Strobe signal Write Enable Signal Clock Enable Signal for SDRAM Chip Select Signal, one for each SDRAM channel CS[0] => channel X CS[1] => channel Y Data Bus, connect to DQ at the SDRAM device Output Mask, connect to DQM at the SDRAM device
D[31:0] BE[3:0]
IN/OUT OUT
2.4
Registers
The following registers are used for configuration and operation of the TMPR3916 memory channels 2 to 5 via MEMC. For channels 0 and 1 (SDRAM) refer to section 2.5.4. Device
MEMC
Register (short name)
RCCR2 RCCR3 RCCR4 RCCR5
Physical Address (hex)
1C02 0008H 1C02 000CH 1C02 0010H 1C02 0014H 1C02 8000H 1C02 8004H 1C02 8008H 1C02 800CH
Function
ROM Control Register Channel 2 ROM Control Register Channel 3 ROM Control Register Channel 4 ROM Control Register Channel 5 SDRAM Configuration Register SDRAM Base Address Register SDRAM Address Mask Register SDRAM Timing Register
SDRAM
DCCR DCBA DCAM DCTR
2-6
Preliminary
Chapter 2 Memory Controller (MC)
2.5
SDRAMC Functions
Address Translation
The table below shows the different memory organizations that have been considered during the controller design and that can be used for each of the two memory channels. Channel Size Mapped G-Bus Toshiba Device Organizations (for one channel) Address Bits Number (Devices x Banks x Rows x Columns x Bits)
8 Mbyte 16 Mbyte 32 Mbyte 64 Mbyte [22:2] [23:2] [24:2] [25:2] TC59S6432 TC59S6416 TC59S6408 TC59SM716 TC59S6404 TC59SM708 TC59SM816 TC59SM704 TC59SM808 TC59SM804 1 x 4 x 2 K x 256 x 32 (SDRAM, 64 Mbit) 2 x 4 x 4 K x 256 x 16 (SDRAM, 64 Mbit) 4 x 4 x 4 K x 512 x 8 (SDRAM, 64 Mbit) 2 x 4 x 4 K x 512 x 16 (SDRAM, 128 Mbit) 8 x 4 x 4 K x 1 K x 4 (SDRAM, 64 Mbit) 4 x 4 x 4 K x 1 K x 8 (SDRAM, 128 Mbit) 2 x 4 x 8 K x 512 x 16 (SDRAM, 256 Mbit) 8 x 4 x 4 K x 2 K x 4 (SDRAM, 128 Mbit) 4 x 4 x 8 K x 1 K x 8 (SDRAM, 256 Mbit) 2 x 4 x 8 K x 1 K x 16 (SDRAM, 512 Mbit) 8 x 4 x 8 K x 2 K x 4 (SDRAM, 256 Mbit) 4 x 4 x 8 K x 2 K x 8 (SDRAM, 512 Mbit)
2.5.1
128 Mbyte
[26:2]
256 Mbyte
[27:2]
Therefore, SDRAMC supports the following memory organizations: Banks: 2 or 4 Rows: 2 K, 4 K, 8 K Columns: 256, 512, 1 K, 2 K The following table shows address translation of the G-Bus address for supported memory configurations. Organization Organization Organization Address Mapping Address Mapping Address Mapping Column Size Row Size Bank Size ColAddr RowAddr BankAddr
256 2K 4K 8K 512 2K 4K 8K 1024 2K 4K 8K 2048 2K 4K 8K 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 GAO[9:2] GAO[9:2] GAO[9:2] GAO[10:2] GAO[10:2] GAO[10:2] GAO[11:2] GAO[11:2] GAO[11:2] GAO[12:2] GAO[12:2] GAO[12:2] GAO[20:10] GAO[21:10] GAO[22:10] GAO[21:11] GAO[22:11] GAO[23:11] GAO[22:12] GAO[23:12] GAO[24:12] GAO[23:13] GAO[24:13] GAO[25:13] GAO[21] GAO[22:21] GAO[22] GAO[23:22] GAO[23] GAO[24:23] GAO[22] GAO[23:22] GAO[23] GAO[24:23] GAO[24] GAO[25:24] GAO[23] GAO[24:23] GAO[24] GAO[25:24] GAO[25] GAO[26:25] GAO[24] GAO[25:24] GAO[25] GAO[26:25] GAO[26] GAO[27:26]
Note: GAO (G-Bus Address Output) refers to the physical address of the internal system bus.
2-7
Preliminary
Chapter 2 Memory Controller (MC) 2.5.2 SDRAM Controller Function / Bank Interleaving
The SDRAMC module functions as an advanced DRAM controller for synchronous DRAM. The TMPR3916 SDRAMC is "advanced" compared to regular SDRAM controllers in the way that it is capable of handling two different MCU busses at the same time. SDRAM memory devices are usually organized in 4 different banks. All of these banks contain a high-speed static RAM memory buffer, which allows fast sequential access once a DRAM memory row has been sensed into these buffers. The sensing of the DRAM memory row and the rewriting of the sensed row are major contributors to the total duration of each memory access. The following picture shows the benefits of the dual-bus structure:
Single G-Bus SDRAM Controller
Command DQ (Output) GBusA Start GBus A Data
MCU Access QA1 QA2 QA3 QA4 Video/DMA Access QB1 QB2 QB3 QB4 NOP ACTV NOP A NOP READ NOP A NOP NOP PCHG NOP A NOP NOP NOP ACTV NOP B NOP READ NOP B NOP PCHG B
QA1
QA2
QA3
QA4
QB1
QB2
QB3
QB4
Dual G-Bus SDRAM Controller
Command DQ (Output) GBusA Start GBus A Data GBus B Start GBus B Data
MCU Access QB1 QB2 QB3 QB4 QA1 QA2 QA3 QA4 NOP ACTV NOP A NOP READ ACTV PCHG READ NOP NOP NOP NOP A B A B NOP PCHG B
QA1
QA2
QA3
QA4
QB1
QB2
QB3
QB4
Video/DMA Access
Figure 2.5.1 Benefits of Dual-Bus Structure A regular SDRAM memory controller with only one MCU-bus interface will connect both the MCU and the video-controller on one bus. By transferring the bus-ownership both components access the external DRAM memory. Typically, the SDRAM controller is able to work with only one address at the same time. It will not know the address for the next access before the previous transfer has been completed. A dual G-Bus memory controller always knows the state and address of both busses. Therefore, it is possible to work with both addresses at the same time. The dual G-Bus structure can only be effectively used, if the following condition is met: The two busses should utilize either different banks of the same channel or two different channels.
2-8
Preliminary
Chapter 2 Memory Controller (MC)
This means for example that the frame-buffer for the video-controller and the program memory accessed by the MCU should be located in different memory banks. If the condition is not met for two consecutive addresses, the controller needs to precharge the bank first and it has to wait for the precharge-to-active-latency before it can start with the access on the second MCU-bus. A memory throughput gain of up to 40 % can be achieved, if software allows the simultaneous utilization of several SDRAM banks.
2.5.3
Self-Refresh Mode
The SDRAM controller also offers support for the SDRAM self-refresh-mode. In self-refresh mode, the connected SDRAM devices maintain data retention without clock-supply and without the requirement of auto refresh cycles. The self-refresh mode significantly lowers the power consumption of the connected memory devices. Self-refresh mode is entered with the assertion of the SRM bit in the DCCR register. The connected SDRAM channels and the SDRAM controller need to be enabled during this operation. Upon assertion of this flag, SDRAMC will enter the self-refresh-mode by issuing a self-refresh-entry command. SDRAMC will remain in self-refresh mode until the deassertion of the SRM flag. The SDRAMC logic guarantees a minimum time of APL latency cycles in self-refresh mode. The SRM flag can be cleared in two different ways, by either writing the bit to "0" or by conducting an access to mapped memory space. After clearing the SRM flag, the CKE signal is asserted to exit the self-refresh mode. The SDRAM controller issues NOP commands for the number of cycles specified by the ARL setting. After this, a regular auto refresh cycle will be conducted to finalize the sequence.
2-9
Preliminary
Chapter 2 Memory Controller (MC) 2.5.4 Configuration Registers
Overview SDRAMC is configured using a total of four configuration registers. These configuration registers reside in the SDRAMC configuration area. The configuration registers can be accessed using byte, halfword and word type accesses. Following, the two memory channels are numbered X (CS0) and Y (CS1). Each channel can be set up using its own memory configuration. The registers RSX, CSX and BSX are used to set up the configuration for memory channel X. The registers RSY, CSY and BSY are used to setup the configuration for memory channel Y. Control Register (DCCR)
Bit Name Bit Name Bit Name Bit Name 7 15 RSY 6 5 CEN 23 RSX 14 13 CSY 4 22 21 CSX 12 20 19 BSX 11 BSY 3 PRIO 2 18 10 17 ACCD 9 1 ENA 0 PWR 16 SRM 8 31 30 29 28 27 26 25 24
Bit
31:24 23:22
Name
RSX Wired to zero
Function
Reset Value
0 00
R/W
R R/W
Row Size for channel X The RSX, CSX and BSX fields are used to specify the organization of memory channel X. 00 = 2 K 01 = 4 K 10 = 8 K 11 = Invalid setting Column Size for channel X Number of Columns 00 = 256 01 = 512 10 = 1 K 11 = 2 K Bank Size for channel X Number of Banks 0 = 2 banks 1 = 4 banks Wired to zero Acceleration Disable Disabling dual G-Bus accelerations significantly lowers system performance. Therefore, this mode is meant to be used as fault mode only. 0 = All Accelerations Enabled 1 = Prevents Dual G-Bus Accelerations
21:20
CSX
00
R/W
19
BSX
0
R/W
18 17
ACCD
0 0
R R/W
2-10
Preliminary
Chapter 2 Memory Controller (MC)
Reset Value
0
Bit
16
Name
SRM
Function
Self Refresh Mode This register is used to enter and exit the SDRAM self-refresh mode. Self-Refresh mode will automatically be entered, by writing this register to 1. Self-Refresh mode is exited, by writing SRM with a value of 0 or by conducting a read or write access to the SDRAM mapped memory region. CEN or ENA may not be deasserted during self-refresh mode. If self-refresh mode is not utilized, initialize SRM to 0. Row Size for channel Y The RSY, CSY and BSY fields are used to specify the organization of memory channel Y. 00 = 2 K 01 = 4 K 10 = 8 K 11 = Invalid setting Column Size for channel Y Number of Columns 00 = 256 01 = 512 10 = 1 K 11 = 2 K Bank Size for channel Y Number of Banks 0 = 2 banks 1 = 4 banks Wired to zero Memory Channel Enable Channel Y 1 = Enable address decoding for this channel 0 = Disable address decoding for this channel This setting enables and disables the address decoding for the memory channel. A memory channel cannot be accessed, if it is disabled using this bit and G-Bus transactions within the channel's address range will not be answered. Memory Channel Enable Channel X 1 = Enable address decoding for this channel 0 = Disable address decoding for this channel This setting enables and disables the address decoding for the memory channel. A memory channel cannot be accessed, if it is disabled using this bit and G-Bus transactions within the channel's address range will not be answered. G-Bus Priority Setting This bit can be used to prioritize the access of one G-Bus. However, this bit has only a minor impact. In the scenario, the memory controller is in idle state when both G-Busses simultaneously start a G-Bus transaction: 1 = G-Bus X will be serviced with priority 0 = G-Bus Y will be serviced with priority A real prioritization of one G-Bus is not efficient in terms of performance, since it is not possible to utilize the dual G-Bus structure under these circumstances. Additionally, the latency of one G-Bus would become unpredictable. Wired to zero
R/W
R/W
15:14
RSY
00
R/W
13:12
CSY
00
R/W
11
BSY
0
R/W
10:6 5
CEN1
0 0
R R/W
4
CEN0
R/W
3
PRIO
0
R/W
2
0
R
2-11
Preliminary
Chapter 2 Memory Controller (MC)
Reset Value
0
Bit
1
Name
ENA
Function
ENA - Module Enable 1 = Enable Module 0 = Disable Module If SDRAMC is disabled the state-machine of the SDRAM controller is suspended and the controller will remain in the idle state. This also means that connected SDRAMs will not be refreshed and that their contents will be lost. The module should never be disabled during its normal operation. It has to be ensured, that no SDRAM accesses are performed on one of the G-Busses when the module is disabled. For example, SDRAMC should never be disabled in a situation, where read accesses are still performed on the video bus. It is mandatory to disable the GDC before SDRAMC is being disabled. Software should also ensure, that the internal write-buffer has been written to SDRAM memory. Violations to these rules might result in bus hang-ups. PWR - Power-Up Sequence Setting this bit will run the power-up sequence for all connected and enabled memory devices. The power-up sequence is described more closely in the next chapter. This flag can be read to determine the end of the power-up procedure. At the end of the power-up sequence, this bit is automatically cleared by the SDRAM controller state-machine.
R/W
R/W
0
PWR
0
R/W
Base Address Register (DCBA)
Bit Name Bit Name 15 BAY 31 BAX 6 5 22 21 0 16
Bit
31:22
Name
BAX
Function
Base Address Memory Channel X This register is used to define the base address for memory channel X. This address is compared to the upper 10 bits of the physical G-Bus address. Wired to zero Base Address Memory Channels Y The same as for the memory channel X. Wired to zero
Reset Value
0
R/W
R/W
21:16 15:6 5:0
BAY
0 0 0
R R/W R
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Preliminary
Chapter 2 Memory Controller (MC)
Address Mask Register (DCAM)
Bit Name Bit Name 15 AMY 31 AMX 6 5 22 21 0 16
Bit
31:22
Name
AMX
Function
Address Mask Memory Channel X This field is used to mask the base address for memory bank X. 1 = Bit is taken into account during comparison 0 = Bit is don't care for the comparison The base address mask is used to select the memory part of an appropriate size. It is also possible to mirror DRAM memory parts or to protect memory parts using this register. Wired to zero Address Mask Memory Channels Y The same as for memory channels X. Wired to zero
Reset Value
0
R/W
R/W
21:16 15:6 5:0
AMY
0 0 0
R R/W R
Timing Register (DCTR)
Bit Name Bit Name 15 14 APL 13 12 11 RASL 10 9 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RFC 8 CASL 7 6 5 PAL 4 3 2 ARL 1
WRL 0
Bit
31:18
Name
RFC
Function
Refresh Counter Reload Value This field provides the reload value for the internal refresh counter. The refresh counter is implemented as a 14 bit down counter, which reloads and issues a refresh request, every time a value of 0 is reached. This Settings depends on the specified refresh cycle time and number of rows of the connected memory devices:
Reset Value
0x1000
R/W
R/W
Register Value =
Refresh Time Operation Frequency Number of Rows
(Example settings at 60 MHz, counter values / settings in Hex) Time 2 K Row 4 K Row 8 K Row 32 ms 0x03A9 0x01D4 0x00EA 64 ms 0x0752 0x03A9 0x01D4 128 ms 0x0EA4 0x0752 0x03A9
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Preliminary
Chapter 2 Memory Controller (MC)
Reset Value
11
Bit
17:16
Name
WRL
Function
Write Recovery Latency This setting defines the minimum number of cycles, from the point where the last word has been written until the "precharge" command is issued. This setting has to match the write recovery time (tWR) of the selected SDRAM. 00 = 1 cycle 01 = 2 cycles 10 = 3 cycles 11 = 4 cycles Active to Precharge Latency This field and the associated timer is used to ensure the Active to Precharge Latency (tRAS). The register value is used as reload value for an internal down counter. PCHG Latency 000 ..010 = Invalid setting 011 = 3 cycles 100 = 4 cycles 101 = 5 cycles 110 = 6 cycles 111 = 7 cycles RAS Latency This timeframe has to safely match the tRCD time of the selected SDRAM device. The setting defines the number of cycles between providing the row address and the column address. This setting is used as reload value for a 3 bit down counter. 010 = 2 cycles 011 = 3 cycles 100 = 4 cycles 101 = 5 cycles Others = Invalid setting CAS Latency This setting defines the number of clock cycles from the time that the column address is provided (READ, RDA / WRITE, WRA) until the first data is taken/output from/on the SDRAM data bus. During the power-up sequence, this value is programmed into the mode register as it is. For the SDRAM controller this setting is used as a reload value for an internal down counter. CAS latencies of less than 2 cycles are not supported! 010 = 2 cycles 011 = 3 cycles Others = Invalid settings Same Bank Precharge -> Active/Refresh Latency This setting defines the minimum number of cycles from the point where the bank is precharged until it is reused (Activate, Refresh). This timeframe is defined by the tRP time of the selected memory device. This time will not be taken, if a different bank or a different memory device is accessed. 010 = 2 cycles 011 = 3 cycles 100 = 4 cycles 101 = 5 cycles 110 = 6 cycles 111 = 7 cycles Others = Invalid settings
R/W
R/W
15:13
APL
111
R/W
12:10
RASL
011
R/W
9:7
CASL
011
R/W
6:4
PAL
111
R/W
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Preliminary
Chapter 2 Memory Controller (MC)
Reset Value
111
Bit
3:0
Name
ARL
Function
Auto Refresh To Next Command Latency This setting defines the number of clocks, which are taken after an Auto Refresh Command has been issued. This setting is used as a reload value for a down counter. The counter will prevent any active SDRAM commands until it is expired. 0000 = Invalid setting 0001 = 3 cycles 0010 = 4 cycles 0011 = 5 cycles ... ... 1111 = 17 cycles
R/W
R/W
2.5.5
Software Power-Up Sequence
The picture below shows the software flow that is necessary to initialize the module. The SDRAM memory typically requires to be held in reset or disabled state until the internal circuits have stabilized. Software has to ensure that this state is applied for the specified amount of time by not enabling the SDRAM controller during this timeframe. After the configuration registers have been sequentially configured, a power-up cycle needs to be scheduled by writing a "1" value to the PWR bit in the DCCR register. Finally, the SDRAM controller and the utilized channels needs to be enabled to start the initialization. The PWR bit can be read to determine the end of the Power-Up sequence. During the power-up procedure, this flag will be read as "1". It is cleared, when the power-up procedure completes. Software Flow of Initialization:
Reset
Set PWR in DCCR Wait for at least 200 s
Configure Control Register (DCCR)
Enable the module by asserting the ENA bit in DCCR No
Configure Timing Register (DCTR)
PWR cleared? Yes
Configure Address Mapping (DCAM)
DRAM ready for usage
Configure Address Mapping (DCBA)
Figure 2.5.2 SDRAM Power-up Software Sequence Flow Chart
2-15
Preliminary
Chapter 2 Memory Controller (MC) 2.5.6 Address Mask Configuration
The following example provides a step by step approach that shows how to configure base-address and address-masks for a memory channel. For the example it is assumed that two 128 MBit SDRAM devices with 16 Bit connectivity are connected to one of the SDRAM Controller channels. To configure the address mask proceed in the following order: 1. Select a base-address for the memory area to be mapped. In this example, we choose 0x5000_0000 as the physical base address for the memory area to be mapped. Determine how much memory is connected to the memory channel: In this example 2 devices with 16 MBytes each => 32 MByte Determine how many address bits are required to address 33.554.432 Bytes log2 (33554432) = 25 This means that 25 address bits are required for the channel Therefore, the correct address mask is 0xfe00. In this case, the memory area from 0x5000_0000 to 0x51ff_ffff will be mapped to the SDRAM channel. The SDRAM controller will respond only to bus accesses that refer to an address within this area. Starting from this setup also mirror areas and protected areas can be generated: Example for mirroring: An address mask 0x7e00 will map the same physical memory twice to the addresses: 0x5000_0000 - 0x51ff_ffff and 0xD000_0000 - 0xD1ff_ffff Example for protection: An address mask 0xff00 will leave the memory area 0x5000_0000 - 0x50ff_ffff accessible, while the second half 0x5100_0000 - 0x51ff_ffff is protected. Please note that the SDRAM always refers to physical address space, which might differ from the virtual address space used within a computer program.
2. 3.
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Preliminary
Chapter 2 Memory Controller (MC)
Timing Diagrams Basic Read Timing:
CLK
CS*
A
ROW
COLUMN
ROW
BA / A[16:15]
BANK A
BANK A
BANK A
BANK A
CKE
RAS*
CAS*
WE*
DQ / D
Data0
Data1
DQM / BE
CMD
ACT
READ
PCHG
ACT
RASL setting
CASL setting
APL setting
PAL setting
Register settings for this example: RASL = 010 bin, CASL = 010 bin, APL = 100 bin, PAL = 011 bin
Figure 2.5.3 SDRAM Read Access Timing Diagram Basic Write Timing:
CLK
CS*
A
ROW
COLUMN
ROW
BA / A[16:15]
BANK A
BANK A
BANK A
BANK A
CKE
RAS*
CAS*
WE*
DQ / D
Data0
DQM / BE
CMD
ACT
Write
PCHG
ACT
RASL setting
APL setting
PAL setting
WRL setting
Register settings for this example: RASL = 010 bin, CASL = 010 bin, APL = 100 bin, PAL = 011 bin, WRL = 01bin
Figure 2.5.4 SDRAM Write Access Timing Diagram
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Preliminary
Chapter 2 Memory Controller (MC)
Bank Interleaved Read Timing:
CLK
CS*
A
ROW
COLUMN
ROW
COLUMN
BA / A[16:15]
BANK A
BANK A
BANK B
BANK A
BANK B
BANK B
CKE
RAS*
CAS*
WE*
DataA0
DataA1
DataA2
DataA3
DataB0
DataB1
DataB2
DataB3
DQ / D
DQM / BE
CMD
ACT A
READ A
ACT B
PCHG A
READ B
PCHG B
RASL setting
CASL setting APL setting PAL seeting ignored due to bank interleaving cycle
BANK A
RASL setting
CASL setting
BANK B
APL setting
Figure 2.5.5 Read Access Using Bank Interleaving Auto-Refresh Timing:
CLK
CS*
A
ROW
BA / A[16:15]
BANK A
BANK A
CKE
RAS*
CAS*
WE*
DQ / D
DQM / BE
CMD
PCHG
AREF
ACT
PAL setting
ARL setting
Register settings for this example: PAL = 011 bin, ARL = 0010 bin
Figure 2.5.6 Waveform for Auto-Refresh Timing
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Preliminary
Chapter 2 Memory Controller (MC)
Self Refresh Mode Timing:
CL K
CS*
A
BA/ A[ 16: 15]
BANK A
CKE
RAS*
CAS*
WE*
DQ/ D
DQM/ B E
CMD
PCHG
SRM En t r y
SRM Ex i t
AREF
ACT
PAL sett i ng APL Reg
ARL Re g
ARL Re g
Se t t i ng f o r t hi s t e s t c a s e : ARL =0 00 1 b i n
Figure 2.5.7 Timing Diagram for Self Refresh Mode
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Preliminary
Chapter 2 Memory Controller (MC)
2.6
MEMC Function
Channel functionality is specified by applying special values to Channel Control Registers. They must be accessed using 32-bit cycles.
2.6.1
Channel Assignment
TMPR3916 contains the total of four multi-purpose memory controller channels. The following chip-select signals are assigned to these channels: Chip Enable Signal
CS2 CS3 CS4 CS5
Assigned to Channel
MEMC Channel 2 MEMC Channel 3 MEMC Channel 4 MEMC Channel 5 (Boot Channel)
Channel 5 is a special function channel and is used to boot the microprocessor from external devices like SRAM, ROM or FLASH memories.
2.6.2
Channel 5 Boot Function
For the system boot procedure, it can be chosen, whether the system shall be booted from a 16 or 32 bit device. This choice is made by connecting a pull-up or pull-down resistor to the A26/ BOOT16 pin. The value of this pin is latched once during system startup on the rising edge of the reset signal, when the EBIF data bus is tri-stated. Value of A26 / BOOT16 Pin on Rising Edge of Reset
0 1
Boot-function
Channel 5 is 32-bits wide at boot time Channel 5 is 16-bits wide at boot time
2.6.3
Operational Modes
We can distinguish two operational modes depending on the types of memory connected to the channels 2 to 5. These two operational modes lead to two different settings: Flash/SRAM setting and Page Mode ROM setting.
2.6.3.1
Flash/SRAM setting The SRAM and Flash memories cannot be accessed in page mode. Therefore some parameters in the RCCRx (x = 2, 3, 4, 5) control registers assume a particular meaning. The setting of bits RPM is always 00 ("Not configured for page mode"). The RPWT is no longer used as a wait state parameter for second and following accesses in burst mode. In non-page mode RPWT and RWT define together the wait time in the access to the Flash or SRAM. The RWT represents the lower significant bits of the wait time parameter, while RPWT represents the most significant bits.
2-20
Preliminary
Chapter 2 Memory Controller (MC)
When RWT = 0xF and RPWT = 0x3, the ACK* pin becomes an input and the data transaction is completed upon assertion of the ACK* signal by the accessed memory. 2.6.3.2 Page Mode ROM setting Please note the following before setting the registers to drive memories in burst mode. * Normal Sub-mode A channel enters this mode when the following conditions exist: RPM = 00 and (RPWT:RWT[3:0])! = 0x3Fh. In this mode the ACK*/READY pin is an ACK* output and the cycle is terminated based on a 6-bit wait counter. The 6-bit wait counter is the concatenation of the RPWT and RWT fields. Access time can be programmed to allow for 0 to 62 wait states. (Note: (RPWT:RWT[3:0] = 0x3Fh indicates external ACK* sub-mode.) * External ACK* Sub-mode A channel enters this mode when the following conditions exist: RPM =00 and (RPWT:RWT[3:0] = 0x3Fh. In this mode the ACK*/READY pin is an ACK* input and the cycle is terminated by the external device. The ACK* input is synchronized before it is fed to the internal state machine. See section ACK* input timing for more details. * Page Sub-mode A channel enters this mode when the following conditions exist: RPM! = 00. In this mode the ACK*/READY pin is an ACK* output and the cycle is terminated based on either the RPWT or RWT wait counter. The mode specifically targets Page Mode ROMs. During single cycle access, or the first word of a burst access, the 4-bit RWT field determines the access time. The access time can be programmed to allow for 0 to 15 wait states. During subsequent burst cycle accesses, the 2-bit RPWT field determines the access time and can be programmed to allow for 0 to 3 wait states. There are 3 different Page Mode Burst size settings allowed in the RPM field. When the Page Mode burst size is less than the CPU burst size, the channel will break access such that the 4-bit RWT field is always used on the programmed Page Mode boundary. In Page Mode the RWT time must be greater than or equal to the RPWT time or undetermined results may occur. * 16-bit Bus Operation In the case of 16-bit mode if a single cycle is run from the G-Bus that requires a single byte or half word that is contained within one 16-bit word then only a single 16-bit access is run on the external bus. Otherwise two 16-bit accesses are executed externally. In the case of 16bit mode, if a burst cycle is run from the G-Bus, two 16-bit cycles will be run for each of the burst accesses regardless of the fact that the internal byte enable signal is requesting a byte, half word or any other combination of internal byte enable signal that is not a full 32-bit word. In 16-bit mode the maximum channel size is 512 Mbytes.
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Preliminary
Chapter 2 Memory Controller (MC)
* RSHT Option The RSHT option is entered when the RSHT field is non-zero. This option adds the capability of adding setup and hold time between the following signals: Setup ADDR to CE, CE to OE, CE to BE. Hold CE to ADDR, OE to CE, BE to CE. Typically it is used with slow I/O peripherals. All setup and hold times are the same for a given value and are not individually programmable. RSHT mode cannot be used in conjunction with Page Mode. All other modes can incorporate the RSHT mode but are restricted such that burst accesses are not allowed.
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Preliminary
Chapter 2 Memory Controller (MC)
ROM Channel Control Register 2-4 (RCCR2-RCCR4)
Bit Name Bit Name 15 14 13 12 11 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RBA 10 RCS 9 8 7 RBS 6 5 RBC 4 3
RPM 2
RPWT 1 RSHT 0
RWT
RME
Bit
31:20 19:18
Name
RBA RPM
Function
Base Address Designates the physical base address. Page Mode, Page Size Designates the page size of channel word burst page mode. 00 = Not configured for page mode 01 = 4-word burst page mode 10 = 8-word burst page mode 11 = 16-word burst page mode Page Mode Wait Time Designates a 2-bit wait state counter in Page Mode for consecutive burst accesses. 00 = 0 wait cycles 01 = 1 wait cycle 10 = 2 wait cycles 11 = 3 wait cycles Designates the upper 2 bits of a 6-bit wait state counter for all other modes except External ACK mode. External ACK mode is entered when all bits of RPWT and RWT are set to 1. (Refer to "RWT") Normal Mode Wait Time Designates a 4-bit wait state counter in Page Mode for single cycles or initial burst cycle. 0000 = 0 wait cycles 0001 = 1 wait cycle 0010 = 2 wait cycles : : 1111 = 15 wait cycles Designates the lower 4-bits of a 6-bit wait state counter in all other modes except External ACK mode. External ACK mode is entered when all bits of RPWT and RWT are set to 1. RPWT [1:0] : RWT [3:0] 000000 = 0 wait cycles 000001 = 1 wait cycle 000010 = 2 wait cycles : : 011110 = 30 wait cycles 011111 = 31 wait cycles : : 111110 = 62 wait cycles 111111: External ACK* mode Note: When PM=00, if setting RPWT: RWT = 0x3f, the wait number doesn't become the longest in ACK* output mode but the mode becomes ACK* input
Reset Value
0x000 00
R/W
R/W R/W
17:16
RPWT
00
R/W
15:12
RWT
0000
R/W
2-23
Preliminary
Chapter 2 Memory Controller (MC)
Reset Value
0000
Bit
11:8
Name
RCS
Function
Channel Size Designates the memory size to be assigned. 0000 = 1 M byte 0110: 64 M bytes 0001 = 2 M bytes 0111: 128 M bytes 0010 = 4 M bytes 1000: 256 M bytes 0011 = 8 M bytes 1001: 512 M bytes 0100 = 16 M bytes 1010: 1 G bytes 0101 = 32 M bytes 1011-1111: Reserved In 16-bit mode the maximum channel size allowed is 512M Bytes. Bus Size Sets up the memory bus width of Channel 2. 0 = 32-bit bus size 1 = 16-bit bus size Wired to zero Byte Enable Control This bit determines whether the Byte Enable signals (BE[3:0]) are asserted on read and write accessed or only on write accesses. 0 = Byte Enables active on read and write accesses 1 = Byte Enables active only on write accesses Wired to zero Master Enable Enables channel. 0 = Channel is disabled 1 = Channel is enabled Setup/Hold Wait Time Selects the number of wait states between address and chip enable signal, chip select signal and write enable/output enable signal. 000 = Disabled 001 = 1 wait 010 = 2 wait 011 = 3 wait : : 111 = 7 wait Burst access and Page Mode are not allowed if this bit field is nonzero.
R/W
R/W
7
RBS
0
R/W
6 5
RBC
0 0
R R/W
4 3
RME
0 0
R R/W
2:0
RSHT
000
R/W
2-24
Preliminary
Chapter 2 Memory Controller (MC)
ROM Channel Control Register 5 (RCCR5) The channel 5 is used as boot channel. Note that the pin A26 / Boot16 has an impact on the bus width setting of the connected boot device. The RCCR5 has the same bit functions like RCCR2 to RCCR4. Only reset-values differ. For detailed description of function, please see RCCR2-RCCR4.
Bit Name Bit Name 15 14 13 12 11 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RBA 10 RCS 9 8 7 RBS 6 5 RBC 4 3
RPM 2
RPWT 1 RSHT 0
RWT
RME
Bit
31:20 19:18 17:16
Name
RBA RPM RPWT
Reset Configuration
Base Address (default: 0x1FC0 0000) Page Mode, Page Size (default: no page mode) The device is not configured for page mode (RPM bits). This means that RPWT and RWT are combined to one counter value for the wait state generation. The wait state counter is set to 64 wait states, that can be reduced in the boot routine to a value that fits to the connected device. Normal Mode Wait Time (default: 14 wait cycles) Channel Size (default: 4 Mbyte) Bus Size (configuration is latched from A26/BOOT16 pin) Wired to zero Byte Control (default: byte enables only active on write access) Wired to zero Master Enable (default: enabled) Setup/Hold Wait Time (default: disabled)
Reset Value
0x1FC 00 11
R/W
R/W R/W R/W
15:12 11:8 7 6 5 4 3 2:0
RWT RCS RBS RBC RME RSHT
1110 0010 BOOT16 Pin 0 0 0 1 000
R/W R/W R/W R R/W R R/W R/W
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Preliminary
Chapter 2 Memory Controller (MC) 2.6.4 Timing Diagrams
Single Read Access:
SYSCLK
CSx
A
Address 0
BE
BE 0
RD
WR
BSTART
LAST
BURST
D
Data 0
ACK
BUSERR
data latched RWT wait states
Single Read with RWT = 01 (1 wait state)
Figure 2.6.1 SRAM/ROM/Flash Single Read Access Timing Single Write Access:
SYSCLK
CSx
A
Address 0
BE
BE 0
RD
WR
BSTART
LAST
BURST
D
Data 0
ACK
BUSERR
RWT wait states
Single W rite with RWT = 01 (1 wait state)
Figure 2.6.2 SRAM/ROM/Flash Single Write Access Timing
2-26
Preliminary
Chapter 2 Memory Controller (MC)
Page Mode Read Access:
SYSCLK
CSx
A
Address 0
Address 1
Address 2
Address 3
BE
0000
RD
WR
BSTART
LAST
BURST
D
Data 0
Data 1
Data 2
Data 3
ACK
BUSERR
data latched RWT wait states RPWT wait states
data latched RPWT wait states
data latched RPWT wait states
data latched
4-word Page-mode with RWT = 01 (1 wait state) and RPWT = 0001 (1 wait state)
Figure 2.6.3 Timing Diagram for SRAM/ROM/Flash Read Access Using Page Mode
External Acknowledge Mode Read Access:
SYSCLK
CSx
A
Address 0
BE
BE 0
RD
WR
BSTART
LAST
BURST
D
Data 0
ACK
BUSERR
data latched
Figure 2.6.4 Waveform for External Acknowledge Mode Read Access Timing
2-27
Preliminary
Chapter 2 Memory Controller (MC)
External Acknowledge Mode Write Access:
SYSCLK
CSx
A
Address 0
BE
BE 0
RD
WR
BSTART
LAST
BURST
D
Data 0
ACK
BUSERR
Figure 2.6.5 Waveform for External Acknowledge Mode Write Access Timing
External Acknowledge Mode Bus Error:
SYSCLK
CSx
A
Address 0
BE
BE 0
RD
WR
BSTART
LAST
BURST
D
Data 0
ACK
BUSERR
data latched
Figure 2.6.6 Bus Error During External Acknowledge Mode Timing
2-28
Preliminary
Chapter 2 Memory Controller (MC)
16 bit Read Access:
SYSCLK
CSx
A
Address 0
Address 1
BE
1100
1111
1100
RD
WR
BSTART
LAST
BURST
D
Data 0
Data 2
ACK
BUSERR
data latched
data latched
Figure 2.6.7 SDRAM Timing Diagram for 16-Bit Read Access
16 bit Write Access:
SYSCLK
CSx
A
Address 0
Address 1
BE
1100
1111
1100
RD
WR
BSTART
LAST
BURST
D
Data 0
Data 2
ACK
BUSERR
Figure 2.6.8 SDRAM Timing Diagram for 16-Bit Write Access
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Preliminary
Chapter 2 Memory Controller (MC)
2-30
Preliminary
Chapter 3 Graphics Display Controller (GDC)
3.
Graphics Display Controller (GDC)
The graphics display controller contains the following characteristics: * * Supports SDRAM and SRAM frame buffer Burst mode for reading on SDRAM Supports four-layer overlay display function using hardware processing Layer A/E: Map mode (256 colors) - referred to as layer A, Picture mode (65,536 colors) - referred to as layer E Layer B: Map mode (one of the 256 colors is transparent) Layer C: Map mode (one of the 16 colors is transparent) Layer D: Map mode (one of the 16 colors is transparent) Displaying layers A and E together is not possible. Layer D screen size can be set independently of the other layer sizes. Incorporates a 544 entries color palette (256 colors x two layers and 16 colors x two layers). Display control: Non-interlaced scanning Smooth scrolling (vertical and horizontal) for layers A, B, C and D Generates and outputs synchronization signals (HSYNC, VSYNC / CSYNC), also supports control by external synchronization signal input. Both digital and analog RGB signal output Dot clock: Supports internal and external dot clock
*
*
3-1
Preliminary
Chapter 3 Graphics Display Controller (GDC)
3.1
GDC Structure
Display Screen
The TMPR3916 can display four layers, overlaid in the following order: A/E, B, C and D. Top layer is D (see Figure 3.1.1). Displaying layers A and E together is not possible because these layers use the same resources except for color palette and dot buffer. The blank signal BLK enables the display data output. The layer active signals LA, LB, LC and LD activate each layer. Layer D screen size can be set independently of the other layer sizes. Layer A can be switched between Map mode and Picture mode (then called layer E). Use the LPA bit of the display control register (DCR) to switch the modes.
3.1.1
Layer D
LD data D:
(0),
1 Next layer displayed
Layer D displayed
Layer C
LC data C:
(0),
1 Next layer displayed
Layer C displayed
Layer B LB data B: (0), 1 Next layer displayed Layer A/E LA, LPA data A/E: Lx data x = 1 Lx data x = 0 Lx data x x : Display : No display (transparent) : Bit in display control register : Layer x display data : A/E, B, C, D Layer A/E displayed Layer B displayed
Figure 3.1.1 Layer Arrangement As can be seen in the figure above layer A/E will always be displayed if all other activated layers contain transparent dots at the current location. Therefore it is recommended to always use one of these two layers to prevent the system from reading dots in an undefined background. For display dimensions the following restrictions apply: Layers A/E, B and C shall be configured at least 64 dots wide horizontally, layer D should have 16 dots minimum. In vertical direction no restriction exists.
3-2
Preliminary
Chapter 3 Graphics Display Controller (GDC) 3.1.2 Frame Buffer
The TMPR3916 supports SDRAM and SRAM as frame buffer. The GDC uses separated address generators for each of its four layers A/E, B, C, and D. It can specify the A/E, B, C, or D layer display data address area by writing the data to the start address register (SARx, where x stands for: A/E, B, C, D), the memory width register (MWRx), the horizontal display start register (HDSR) and the horizontal display end register (HDER). The HDSR and HDER are stored as one value in the horizontal display start end register (HDSER).
32 bit frame buffer MWRx SARx
1st line SARx
SARx + MWRx
2nd line SARx + MWRx
HDER - HDSR frame buffer
(N+1) th line
SARx + N MWRx
Figure 3.1.2 Frame Buffer Data The SARx stores the address of the upper-left corner's dot belonging to layer x. The MWRx stores the offset value to be added to the contents of SARx to get the address of the left-most pixel of the following line. It is not allowed to store the last dot of one line and the first dot of the next line within one memory word as shown below. The TMPR3916 dot data structure in the frame buffer is as follows: In map mode these values are addresses for color palette. In picture mode these values represent the displayed colors. Data Length Per Dot
Map mode C/D Map mode A/B Picture mode 4 bits 8 bits 16 bits
Active Level
Layers C, D Layers A, B Layer E
# Colors
16 256 64K
Accordingly, the data structure for each word is as follows. Bits
Map mode C/D Map mode A/B Picture mode
31:28
Dot 1
27:24
Dot 2
23:20
Dot 3
19:16
Dot 4
15:12
Dot 5 Dot 3
11: 8
Dot 6 Dot 2
7:4
Dot 7 Dot 4
3:0
Dot 8
Dot 1 Dot 1
Dot 2
3-3
Preliminary
Chapter 3 Graphics Display Controller (GDC)
The minimum value to be stored in MWRx is equal to the number of dots per line in the frame buffer divided by 4 (in case of layers A and B, 8 for C and D and 2 for layer E) and rounded to the next greater integer value (MWRx stores numbers of 32 bit words). In practice, it is advisable to have a certain space between two adjacent lines. Therefore the practical memory size is larger than the one requested to cover just one layer. The frame buffer contents represent the address of the color palette which contains the displayed colors for the respective layer:
32 bit frame buffer 16 bit-wide colour palette
Line 1 Dot 1
Line 1 Dot 2
Line 1 Dot 3
Line 1 Dot 4
Line 1 Dot n-2
Line 1 Dot n-1
Line 1 Dot n
Line N Dot 1
Line N Dot 2
Line N Dot 3
Line N Dot 4
Line N Dot n-2
Line N Dot n-1
Line N Dot n To digitalout or VIEWDAC
Figure 3.1.3 Frame Buffer and Color Palette in Case of Layers A or B In case of layers C and D, the contents of register MWRx must be adjusted taking into consideration that there are 8 dots in a 32 bit word. Therefore the minimum value is given by the number of dots in a line divided by 8.
32 bit frame buffer 16 bit colour palette
Line 1 Dot 1
Line 1 Dot 2
Line 1 Dot 3
Line 1 Dot 4
Line 1 Dot 5
Line 1 Dot 6
Line 1 Dot 7
Line 1 Dot 8
Line 1 Dot n-2
Line 1 Dot n-1
Line 1 Dot n
Line N Dot 1
Line N Dot 2
Line N Dot 3
Line N Dot 4
Line N Dot 5
Line N Dot 6
Line N Dot 7
Line N Dot 8
Line N Dot n-2
Line N Dot n-1
Line N Dot n
To digitalout or VIEWDAC
Figure 3.1.4 Frame Buffer and Color Palette in Case of Layers C or D In case of layer E, each 32 bit word is storing the data of 2 dots. So the minimum number to store in MWRA (E layer uses A layer registers) is equal to the number of dots in a line divided by 2. No color palette is needed for layer E.
3-4
Preliminary
Chapter 3 Graphics Display Controller (GDC)
32 bit frame buffer Line 1 Dot 1 Line 1 Dot 2
Line 1 Dot n
Line N Dot 1
Line N Dot 2 To digitalout or VIEWDAC
Line N Dot n
Figure 3.1.5 Frame Buffer in Case of Layer E The number in MWRx is always rounded to the higher integer. Some display devices do colour calibrations during synchronization periods. That is why the graphics display controller outputs black level as analog output from VIEWDAC while HDISP=0. For digital output this value is stored in register PA (see PORT module) with respect to the output mode (dot or pixel). As a result the PA register has to be initialized with the correct value (reset value: 0x00h).
3-5
Preliminary
Chapter 3 Graphics Display Controller (GDC) 3.1.3 Display Control Signal
The GDC block generates and outputs the synchronization signal (HSYNC, VSYNC, and CSYNC). The display uses non-interlaced scanning.
HCR HDER + 8 VSYNC*
HDSR + 8 HSYNC*
HSWR VDSRR VSWR
HDSR + 9
HDER + 8
dot data display area VDSR + 1 VDER
VDER
VCR
blanking area
Figure 3.1.6 Display Timing The GDC block can select and output a separated synchronization (HSYNC*, VSYNC*) or a composite synchronization (CSYNC*) signal. The composite CSYNC* is the EX-NOR (exclusive nor) signal of HSYNC* and VSYNC*.
HSYNC* VSYNC* CSYNC*
Figure 3.1.7 CSYNC* Timing In positive mode the composite CSYNC is the EX-OR (exclusive or) signal of HSYNC and VSYNC.
HSYNC VSYNC CSYNC
Figure 3.1.8 CSYNC Timing When HSYNC and VSYNC are in Positive Mode The DCR bit CSEL enables composite synchronization signal output. The bit NSYNC enables using synchronization signals in positive mode. Externally separated synchronization signals can also be used for input. Set using the ESYNC bit of the DCR.
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Note that the use of external synchronization signals needs processing time. Therefore the input signals HSYNC and VSYNC are delayed internally. To compensate this delay, set the horizontal display-related registers -3, the vertical display-related registers need not be changed. For positive mode set the horizontal display-related register -6 and the vertical display-related register -2. When using external HSYNC and VSYNC signals, the horizontal synchronization pulse width (HSWR), vertical synchronization pulse width (VSWR), horizontal cycle register (HCR) and vertical cycle register (VCR) settings are invalid. External composite synchronization signals cannot be processed by the TMPR3916. Please note also that due to internal data structures HDS and HDE are automatically incremented by 8 so that the effective values are HDS+8 and HDE+8.
3.1.4
Dots and Pixels
The GDC is able to support both, dot and pixel on digital output. The 16-bit data for one dot is divided into R (red), G (green), and B (blue). A pixel represents one of these colors in a 6-bit value. In consequence one dot represents three pixels as shown in the following figure:
15 ~ 11 10 ~ 6 5 ~ 0 16-bit dot data
0/1 R[5:0] G[5:0]
0/1 B[5:0]
6-bit pixel data
Figure 3.1.9 Partitioning RGB Data into Dot and Pixel Data Each six bits of RGB data are input to the 6-bit DAC (three channels) in the GDC. The LSB of R and G transmitted to the DAC data are always fixed to zero. In dot mode (DCR[3] = 0) the GDC supports dots on the digital RGB port (PIO[15:0]) and dot clock on the DOTCLK port. In pixel mode (DCR[3] = 1) the GDC supports pixels on the lower 6 ports of the digital RGB port (PIO[5:0]) and pixel clock on the DOTCLK port. Within the pixel mode the LSB of R and G are equal to bit 4 of the DCR register (DCR[4]).
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3.1.4.1 Dot Clock The dot clock is the reference clock for graphics data output. It is also used to determine the screen size, for example, of each layer. Use the following formula to select the dot clock: Dot clock speed (MHz) = number of display dots per line (including non visible dots) horizontal display period (s)
Note that the internal circuit imposes the following restriction: dot clock speed (MHz) < 1/2 SYSCLK. The dot clock can be provided internally as a derivative of the system clock. The divisor is defined by DCKPS (see Display Control Register (DCR)) and can be set to 4, 6, 8, ..., 24. Therefore frequencies of 2.5 MHz up to 15 MHz can be reached when using the internal dot clock. Default setting for DCKPS is 0x4h for a dot clock of 6 MHz. Alternatively the dot clock may be input via the DOTCLK pin.
3.1.5
Color Palette
In Map mode, each dot can be set for 16 colors using layer C or D and 256 colors using layer A or B. By using the color palette, any 16 or 256 colors respectively can be selected from among the 65,536 colors. The color palette can be set independently for each layer (A, B, C or D). One of the defined colors is transparent for layers B, C and D. It must not be used if no background layer is activated. In Picture mode (layer E), the TMPR3916 can display up to 65,536 colors. The dot data are directly defined at the frame buffer and therefore no color palette is necessary. When programming values to CLUT entries the upper 16 bits of the bus represent the color value, the lower 16 data bits are ignored. Example: For programming entry #7 in layer A's color look-up table to a color with a red part of R = 20, a green pixel G = 23 and a blue one of B = 48, load 0xA5F00000 into memory location 0x1C05081C. The following table shows the color palette structure: Palette Name
CPLTA
Layer
A
Number of Colors
256 colors
Color Palette No.
0 1 : 255 0 1 : 255 0 1 : 15 0 1 : 15
Address
1C05 0800 1C05 0804 : 1C05 0BFC 1C05 0C00 1C05 0C04 : 1C05 0FFC 1C05 0180 1C05 0184 : 1C05 01BC 1C05 01C0 1C05 01C4 : 1C05 01FC
Color Specification
free defined color 0 free defined color 1 : free defined color 255 transparent free defined color 0 : free defined color 254 transparent free defined color 0 : free defined color 14 transparent free defined color 0 : free defined color 14
B
CPLTB
255 colors
C
CPLTC
15 colors
D
CPLTD
15 colors
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3.2
Scrolling
There are two different ways of scrolling when using the TMPR3916's graphics display controller: Smooth scrolling and some kind of register scrolling. Smooth scrolling is done by changing the start address of graphics data in memory (SARx). The layers in TMPR3916 have different resolutions in colour depth. That is why the number of dots per word changes from layer to layer. Therefore the address of the next dot for display differs. This implies different handling of smooth scrolling in the different kinds of layers. The easiest implementation can be reached using layers C and D. It is also the type of implementation this document starts with. Following is the description for layers A and B. Register scrolling is another special type of scrolling a layer by changing the values for horizontal and vertical display start and end. As layers A, B, C and E have common settings for display size and are normally fixed to the display's maximum settings, this scrolling type only applies to layer D. The related registers are HDSERD, VDSRD and VDERD. The algorithms following are based on C syntax for documentation. They also imply just one step at a time in one direction. For moving in several directions at the same step the related algorithm has to be executed for each direction. For example, if scrolling to the left and up is wanted, two runs of the algorithm are needed - one for "LEFT", one for "UP". It is assumed that only four directions have been defined: LEFT, RIGHT, UP and DOWN. This is why the "UP" decision automatically branches into "DOWN" case if false.
3.2.1
Smooth Scrolling
Scrolling Layers C and D For smooth scrolling three bits are reserved in start address register (SARx). As layer C and D both consist of data with eight dots per word and this is the maximum amount of differing addresses that can be generated using three bits for coding, no problem occurs for these layers: Just add (subtract) to (from) SARx the amount of dots you want to use as offset for smooth scrolling to the left (right) or respectively up (down). The related algorithm is shown in the following diagram:
LAYER_C True False
3.2.1.1
newSARx = SARC MWRx = MWRC >> 15
LEFT True RIGHT True
newSARx = SARD MWRx = MWRD >> 15
False
False UP True False
newSARx += offset newSARx -= offset
newSARx += MWR * offset * 4
LAYER_C True
newSARx -= MWR * offset * 4
False
SARC = newSARx
SARD = newSARx
Example: For scrolling a picture located at 0x50010024 (SARx: 0xA0020048) to the left by one dot simply add 0x01 to the latter value: 0xA0020049 is the correct start address register value for the next picture (physical: 0x50010024). Note that the least significant bits in this start adress register
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are not related to the address counter part (AC) but to this smooth scrolling feature. This leads to a dot offset of 1 in the SS register part, so that the dot read as next is located at 0x50010025. 3.2.1.2 Scrolling Layers A and B For working on layers A and B the application of smooth scrolling becomes a little more difficult: One word contains data of four dots, of which the number can be coded by using just two of the three bits reserved in SARx. The algorithm shown in the following diagram is to be used:
LAYER_A True False
newSARx = SARA MWRx = MWRA >> 15 preSARx = newSARx & 0x00000007
LEFT True RIGHT True
newSARx = SARB MWRx = MWRB >> 15
False
False UP True False
preSARx += offset preSARx -= offset
preSARx += MWR * offset * 4 preSARx -= MWR * offset * 4
True
preSARx[2] != newSARx[2]
False
True
preSARx[2] != newSARx[2]
False
newSARx += MWR * offset * 4 newSARx += 8 newSARx -= 8
newSARx -= MWR * offset * 4
newSARx = (newSARx & 0xfffffff8) | (preSARx & 0x00000003)
LAYER_A True False
SARA = newSARx
SARB = newSARx
Example: For scrolling a picture located at 0x50010024 (SARx: 0xA0020048) to the right by four dots do the following: 1. 2. 3. 4. 5. 6. 7. newSARx = 0xA0020048 MWRx = 0x-------- (not needed for this example) preSARx = 0x00000000 preSARx = 0xFFFFFFFC newSARx = 0xA0020044 newSARx = 0xA0020044 SARA = 0xA0020044
This new entry for start address register results in a physical bus address of 0x50010020, which is the memory address located before the one read first in the last step. The smooth scrolling bits show an offset of 0 so in the end the first dot read is located at 0x50010020, too. Please be aware of the relationship of adding or subtracting the extra offset 0x08 to the scrolling direction.
3.2.2
Register Scrolling
This scrolling type is implemented easily: Just change the values of the start and end registers in horizontal and vertical direction using the projected dot offset:
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HDSERD = HDSERD + ((horoffset << 16) + horoffset) VDSRD = VDSRD + (vertoffset << 16) VDERD = VDERD + (vertoffset << 16)
Note:
For register scrolling the offset handling is kind of reversed in comparison to smooth scrolling. For scrolling a layer to the right the coordinate of the first visible dot has to be incremented. For scrolling a picture in a layer to the right the start address has to be decremented.
Example: Start values: * * * * Horizontal start: Horizontal end: Vertical start: Vertical end: dot 34 dot 50 dot 42 dot 58
For moving layer D up by 2 lines and right by 3 dots the following calculation applies: HDSERD = 0x00220032 + 0x00030003 = 0x00250035 VDSRD = 0x002A0000 - 0x00020000 = 0x00280000 VDERD = 0x003A0000 - 0x00020000 = 0x00380000
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3.3
Internal Blockdiagram
dot buffer A, B C, D
dot shifter overlay
color palette
D[31:0] A[31:2] BE[3:0]* display control register horizontal display start register *2 Digital RGB via PIO: [15:0] in dot mode [5:0] in pixel mode dot buffer E 32 16 16
GDCINT*
start address register *4 A&B&C&D
horizontal display end register *2
DAC
memory width register *4 A&B&C&D
vertical display start register *2
analog out ROUT analog out GOUT
vertical display end register *2 horizontal transfer number register *2 A&B&C&D
analog out BOUT timing control
horizontal synchronous pulse width register
HSYNC horizontal cycle register VSYNC/ CSYNC vertical synchronous pulse width register
HDISP
DOTCLK vertical cycle register
Figure 3.3.1 GDC Block Diagram
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3.4
Registers
Overview Short Name
DCR SARA/E SARB SARC SARD MWRA/E MWRB MWRC MWRD HTN HTND HDSER
Address
1C050000 1C050010 1C050014 1C050018 1C05001C 1C050020 1C050024 1C050028 1C05002C 1C050030 1C050034 1C050038 1C05003C 1C050040 1C050044 1C050048 1C05004C 1C050050 1C050054
Name
display control register Layer A/E's start address register Layer B's start address register Layer C's start address register Layer D's start address register Layer A/E's Memory Width register Layer B's Memory Width register Layer C's Memory Width register Layer D's Memory Width register Layer A/E, B, C's horizontal transfer number register Layer D's horizontal transfer number register Layer A/E, B, C's horizontal display start / end register Layer D's horizontal display start / end register horizontal cycle register horizontal synchronization pulse width register vertical cycle register vertical synchronization pulse width register Layer A/E, B, C's vertical display start register Layer D's vertical display start register
Function
Sets the GDC operations. Specifies the start address of layer A/E on the frame buffer. Specifies the start address of layer B on the frame buffer. Specifies the start address of layer C on the frame buffer. Specifies the start address of layer D on the frame buffer. Specifies the line width of layer A/E on the frame buffer. Specifies the line width of layer B on the frame buffer. Specifies the line width of layer C on the frame buffer. Specifies the line width of layer D on the frame buffer. Sets the number of display dots for one line divided by 32. For layers A/E, B, and C. Sets the number of display dots for one line divided by 32. For layer D. Sets the layer's display position and the number of display dots for layers A/E, B, and C. Sets the horizontal display position and the number of display dots for layer D. Specifies the total number of dots within a horizontal cycle. Specifies the horizontal sync signal pulse width using the number of dot clocks. Specifies the total number of lines within a vertical cycle. Specifies the vertical sync signal pulse width using the number of lines. Sets the vertical display start position for layers A/E, B, and C. Sets the vertical display start position for layer D. Sets the vertical display end position for layers A/E, B, and C. The difference VDER - VDSR defines the number of display dots for layers A/E, B, and C. Sets the vertical display end position for layer D. The different VDERD - VDSRD defines the number of display dots for layer D.
HDSERD HCR HSWR VCR VSWR VDSR VDSRD
VDER
1C050058
Layer A/E, B, C's vertical display end register
VDERD
1C05005C
Layer D's vertical display end register
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Display Control Register (DCR)
Bit Name Bit Name Bit Name Bit Name 7 6 5 4 LSB 15 14 31 BLK 23 30 DCK 22 DCKPS 13 12 3 MODE 2 NSYNC 1 CSEL 0 ESYNC 29 ADS 21 28 LPA 20 27 LD 19 HV 11 26 LC 18 BUSERR 10 25 LB 17 VSYNC 9 24 LA 16 HSYNC 8
Bit
31
Name
BLK
Function
0 Blank screen (analog output) 1 Display frame buffer Note: In order to blank the digital outputs the PORT module has to be set to drive the corresponding PIOs. This can be achieved by setting the lower bits of the PAMUX register to logic zero. The data values specified in the corresponding bits of the PA register are output to the PIOs. 0 1 0 1 0 1 0 1 0 1 0 1 Selects external dot clock Selects internal dot clock (divides SYSCLK) Map mode (layer A, 8 bits per dot) Picture mode (layer E, 16 bits per dot) Do not display layer D Displays layer D Do not display layer C Displays layer C Do not display layer B Displays layer B Do not display layer A/E Displays layer A/E
Reset Value
0
R/W
R/W
30 29 28 27 26 25 24 23:20
DCK LPA LD LC LB LA DCKPS
0 0 0 0 0 0 0 0x4
R/W R R/W R/W R/W R/W R/W R/W
Wired to zero.
Dot Clock: 0hex Not allowed 1hex 1/4 system frequency 2hex 1/6 system frequency 3hex 1/8 system frequency 4hex 1/10 system frequency 5hex 1/12 system frequency 6hex 1/14 system frequency 7hex 1/16 system frequency 8hex 1/18 system frequency 9hex 1/20 system frequency Ahex 1/22 system frequency Bhex 1/24 system frequency Others 1/10 system frequency These bits are relevant only when DCK = 1. 0 1 Interrupt at VSYNC* Interrupt at HSYNC*
19 18
HV BUSERR
0 0
R/W R/W
0 No bus error occurred since last write access to DCR 1 Bus error on video bus during GDC display data transfer When a bus error occurs on video bus this bit is set to 1. It can only be reset by a write access to DCR (any value for BUSERR bit).
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Reset Value
0
Bit
17
Name
VSYNC
Function
0 Vertical scanning synchronization pulse period 1 Vertical scanning display period Note: In positive mode the synchronization period takes place when VSYNC equals logic 1. 0 Horizontal scanning synchronization pulse period 1 Horizontal scanning display period Note: In positive mode the synchronization period takes place when HSYNC equals logic 1. Wired to zero. 0 1 0 1 0 1 0 1 0 1 Outputs 0 on LSB of R/G in pixel mode Outputs 1 on LSB of R/G in pixel mode Dot mode: Outputs dots and dot clock Pixel mode: Outputs pixels serially and pixel clock Normal mode: Outputs sync signals low active Positive mode: Outputs sync signals high active Outputs VSYNC signal from VSYNC pin Outputs CSYNC signal from VSYNC pin Sets HSYNC and VSYNC pins to output mode Sets HSYNC and VSYNC pins to input mode
R/W
R
16
HSYNC
0
R
15:5 4 3 2 1 0
LSB MODE NSYNC CSEL ESYNC
0 0 0 0 0 1
R R/W R/W R/W R/W R/W
Note:
When outputting a digital RGB signal, you must set bits [15:0] of PAMUX register in module PORT to 1.
Start Address Register A/E, B, C, D (SARA/E, SARB, SARC, SARD)
Bit Name 31 SA 21 20 AC 3 2 1 SS 0
Bit
31:21
Name
SA
Function
Segment Address These bits specify the segment start address of each layer's frame buffer. Address Counter These bits specify the start address within the segment defined by SA of each layer's frame buffer. Dot Position These bits specify the first visible dot within the first word addressed by AC. Note that SS width differs for layer A/B and C/D and does not matter for layer E. The SS[2] bit is not relevant for layers A and B. Display Start Position Layer C/D Layer A/B 000 from dot 1 from dot 1 001 from dot 2 from dot 2 010 from dot 3 from dot 3 011 from dot 4 from dot 4 100 from dot 5 from dot 1 101 from dot 6 from dot 2 110 from dot 7 from dot 3 111 from dot 8 from dot 4 AC & SS specify the display start position for each layer in units of dots. Counting up AC & SS scrolls screen to the left. Counting down AC & SS scrolls screen to the right.
Reset Value
0
R/W
R/W
20:3
AC
0
R/W
2:0
SS
0
R/W
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The specified start address SARx is not the same address as the address on the video bus. The lowest bits (SS bits) are used internally only (!). The differences are described in figure 12:
31 SA[10:0] 21 20 AC[17:0] 3 2 0 SS[2:0] SARx [31:0] logical address Used within GDC only
31 30
20 19
2
0
SA[10:0]
AC[17:0]
video bus address [31:2] physical address
Figure 3.4.1 Logical Address and Physical Bus Address Note: Bit 31 of video bus address is tied to 0.
Memory Width Register A/E, B, C, D (MWRA/E, MWRB, MWRC, MWRD)
Bit Name 31 26 25 MW 16 15 0
Bit
31:26 25:16
Name
MW Wired to zero
Function
Reset Value
0 0
R/W
R R/W
Specifies the line widths of each layer on the frame buffer in oneword units. For example, where the line width is 320 dots: MW = 28hex for layer C and D MW = 50hex for layer A and B MW = A0hex for layer E Wired to zero
15:0
0
R
Horizontal Transfer Number Register (HTN) for layers A/E, B and C
Bit Name 31 21 20 HTN 16 15 0
Bit
31:21 20:16
Name
HTN Wired to zero
Function
Reset Value
0 0
R/W
R R/W
Line Size of Layer A/E, B and C These specify the number of data transfers for one line. Sets the number of display dots for one line divided by 32. Wired to zero
15:0
0
R
Note:
HTN is always rounded to the higher integer value.
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Horizontal Transfer Number Register (HTND) for layer D
Bit Name 31 21 20 HTND 16 15 0
Bit
31:21 20:16
Name
HTND Wired to zero
Function
Reset Value
0 0
R/W
R R/W
Line Size of Layer D These specify the number of data transfers for one line. Sets the number of display dots for one line divided by 32. Wired to zero
15:0
0
R
Note:
HTND is always rounded to the higher integer value. It is for layer D only as layer D may have a different size.
Horizontal Display Start/ End Register (HDSER) for layers A/E, B and C
Bit Name 31 24 23 HDS 16 15 10 9 HDE 0
Bit
31:24 23:16 15:10 9:0
Name
HDS HDE Wired to zero
Function
Reset Value
0 0x2D 0 0x15D
R/W
R R/W R R/W
These specify the horizontal display start position using the number of dot clocks, starting from the HSYNC* signal falling edge. Wired to zero These specify the horizontal display end position using the number of dot clocks, starting from the HSYNC* signal falling edge. Number of dots displayed during one period = HDE - HDS
Note:
The lowest value allowed for HDS and HDE is 2hex. Due to internal data structures effective values are HDS+9 and HDE+8.
Horizontal Display Start/ End Register (HDSERD) for layer D
Bit Name 31 24 23 HDSD 16 15 10 9 HDED 0
Bit
31:26 25:16 15:10 9:0
Name
HDSD HDED Wired to zero
Function
Reset Value
0 0x2D 0 0x15D
R/W
R R/W R R/W
These specify the horizontal display start position using the number of dot clocks, starting from the HSYNC* signal falling edge. Wired to zero These specify the horizontal display end position using the number of dot clocks, starting from the HSYNC* signal falling edge. Number of dots displayed during one period = HDED - HDSD
Note:
The lowest value allowed for HDSD and HDED is 2hex. Due to internal data structures effective values are HDS+9 and HDE+8.
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Horizontal Cycle Register (HCR)
Bit Name 31 26 25 HC 16 15 0
Bit
31:26 25:16
Name
HC Wired to zero
Function
Reset Value
0 0x189
R/W
R R/W
Specifies the total number of dots and dot clocks within one horizontal cycle. HC = horizontal cycle time (s) x dot clock frequency (MHz) Wired to zero
15:0
0
R
Vertical Cycle Register (VCR)
Bit Name 31 26 25 VC 16 15 0
Bit
31:26 25:16 15:0
Name
VC Wired to zero
Function
Reset Value
0 0x107 0
R/W
R R/W R
Specifies total number of lines within one vertical cycle. VC = vertical cycle time (ms) / horizontal cycle time (ms) Wired to zero
Horizontal Synchronous Pulse Width Register (HSWR)
Bit Name 31 23 22 HSW 16 15 0
Bit
31:23 22:16 15:0
Name
HSW Wired to zero
Function
Reset Value
0 0x11 0
R/W
R R/W R
Specifies the horizontal sync signal pulse width using the number of dot clocks. Wired to zero
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Vertical Synchronous Pulse Width Register (VSWR)
Bit Name 31 21 20 VSW 16 15 0
Bit
31:21 20:16 15:0
Name
VSW Wired to zero
Function
Reset Value
0 0x03 0
R/W
R R/W R
Specifies the vertical sync signal pulse width using the number of lines. Wired to zero
Vertical Display Start Register (VDSR) for layers A/E, B and C
Bit Name 31 22 21 VDS 16 15 0
Bit
31:21 21:16 15:0
Name
VDS Wired to zero
Function
Reset Value
0 0x04 0
R/W
R R/W R
These bits specify the vertical display start position using the number of lines, starting from the VSYNC* signal falling edge. Wired to zero
Note:
The lowest value allowed for VDS is 2hex.
Vertical Display Start Register (VDSRD) for layer D
Bit Name 31 26 25 VDSD 16 15 0
Bit
31:26 25:16 15:0
Name
VDSD Wired to zero
Function
Reset Value
0 0x0F6 0
R/W
R R/W R
These bits specify the vertical display start position using the number of lines, starting from the VSYNC* signal falling edge. Wired to zero
Note:
The lowest value allowed for VDSD is 2hex.
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Vertical Display End Register (VDER) for layers A/E, B and C
Bit Name 31 26 25 VDE 16 15 0
Bit
31:26 25:16
Name
VDE Wired to zero
Function
Reset Value
0 0x0F6
R/W
R R/W
These specify the vertical display end position using the number of lines, starting from the VSYNC* signal falling edge. Number of display period lines = VDE - VDS Wired to zero
15:0
0
R
Note:
The lowest value allowed for VDE is 2hex.
Vertical Display End Register (VDERD) for layer D
Bit Name 31 26 25 VDED 16 15 0
Bit
31:26 25:16
Name
VDED Wired to zero
Function
Reset Value
0 0x0F6
R/W
R R/W
These specify the vertical display end position using the number of lines, starting from the VSYNC* signal falling edge. Number of display period lines = VDED - VDSD Wired to zero
15:0
0
R
Note:
The lowest value allowed for VDED is 2hex.
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Chapter 3 Graphics Display Controller (GDC)
3.5
Setting Examples
Display characters: If DOTCLK = 3 MHz Horizontal synchronous cycle is 64 sec/line, Vertical synchronous cycle is 16.678 msec/screen. DCKPS = 0x9, HC = 64 s x 3 MHz = 192 dots, VC = 16.768 ms x 1/64 s = 262 lines.
When displaying a 160-dot x 225-line (32 dots x 32 lines for layer D) picture out of a 368 x 270-frame, and the frame buffer is SDRAM, then SARA=0xA0000000, SARB=0xA0400000, SARC=0xA0800000, SARD=0xA0C00000, MWRA=0x5C, MWRB=0x5C, MWRC=0x2E, MWRD=0x0A. (physical: 0x50000000) (physical: 0x50200000) (physical: 0x50400000) (physical: 0x50600000)
Please note that the defined start addresses are logical addresses. The physical start address is defined as the right shifted logical address and a zero as MSB (see chapter 3.4 `Start address register' Figure 3.4.1). The following are example register settings while internal synchronization signals HSYNC and VSYNC are used: HTN HTND HDS HDE HDSD HDED HC VC HSW VSW VDS VDE VDSD VDED = 0x05, = 0x01, = 0x17, = 0xB7, = 0x37, = 0x57, = 0xC0, = 0x106, = 0x0F, = 0x04, = 0x1B, = 0xFC, = 0x3B, = 0x5B.
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Dot 1 Dot 32 Dot 64 Dot 87 Dot 191 Dot 192
Line 1
display area layers A, B and C
Line 27
Line 59 display area layer D display area layer D Line 91 HDSERD frame buffer layer D display view MWRD
Line 252 memory view blanking area Line 262
frame buffer layer A, B or C display area layer A, B or C display area layer A, B or C
HDSER
MWRA, MWRB or MWRC
Figure 3.5.1 Picture Composition from Frame Buffer to Display Using Example Register Settings
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HTN(5) x 32 = 160 HC = 192 HDE(183) + 8 = 191 HDS (23) + 9 = 32 HDE - HDS = 160 HSW = 15 HSYNC
HDISP
Dot clock 1 15 32 D1 D2 D3 Dn-2 Dn-1 Horizontal invalid data period Display data 191 Dn 192 Horizontal invalid data period
Figure 3.5.2 Display Signals Using Internal Dot Clock and Internal Sync Signals; signals HDISP
(Note that VDISP is an internal signal only)
Chapter 3 Graphics Display Controller (GDC)
and VDISP show active display area in horizontal and vertical direction respectively
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VC = 262 VDE = 252 VDS = 27 VSW = 4 VSYNC VDISP HSYNC 1 Display data 4 vertical invalid data period 27+15 L1 L2 L3
VDE - VDS = 225
252 LN-1 LN
262 vertical invalid data period
Preliminary
Chapter 3 Graphics Display Controller (GDC)
The following are example register settings while external synchronization signals HSYNC and VSYNC are used: Same as internal synchronization signals: HTN HTND VDS VDE VDSD VDED = 0x05, = 0x01, = 0x1B, = 0xFC, = 0x3B, = 0x5B.
Different from settings using internal synchronization signals: HDS HDE HDSD HDED Not relevant registers: HC, VC, HSW, VSW. The display shows the same picture with the selected external synchronization signals HSYNC and VSYNC as in case of internal synchronization signal described before. = 0x14, = 0xB4, = 0x34, = 0x54.
3-24
Preliminary
HTN(5) x 32 = 160 Horizontal cycle time = 64 s HDE(179) + 8 = 191 HDS (19) + 9 = 32 HDE - HDS = 160
external HSYNC
internal HSYNC
HDISP
Dot clock 1 Horizontal invalid data period D1 D2 D3 4 16 32 191 Dn-1 Dn 192 Horizontal invalid data period
Display data
Figure 3.5.3 Display Signals Using Internal Dot Clock and External Sync Signals
(Note that VDISP is an internal signal only)
Chapter 3 Graphics Display Controller (GDC)
3-25
VDE = 252 VDS = 27 external VSYNC internal VSYNC VDISP HSYNC 1 Display data 4 vertical invalid data period 27+15 L1 L2 L3
Vertical cycle time = 16,768 ms
VDE - VDS = 225
252 LN-1 LN
262 vertical invalid data period
Preliminary
Chapter 3 Graphics Display Controller (GDC)
3-26
Preliminary
Chapter 4 Interrupt Controller (INTC)
4.
Interrupt Controller (INTC)
The Interrupt Controller has the following purpose: * * * * show the cause of an interrupt make it possible for software to mask all interrupts, except the NMI handle 3 external interrupt pins handle non-maskable-interrupt (NMI)
4.1
Basic Interrupt Handling
The following list shows the basic steps of an interrupt handler: 1. 2. 3. 4. 5. 6. 7. Change Status Register of CPU to inhibit interrupts with equal or lesser priority. Read Cause Register of CPU to get cause of interrupt. (see also table below) Read IRQR of Interrupt Controller to get more information about interrupt source. Run interrupt routine. Reset interrupt in source. Reset bit of interrupt source in IRQR of Interrupt Controller. Restore Status Register of CPU and jump back to program.
The following table shows all interrupt sources and the corresponding interrupt pin on the CPU: Interrupt Source Interrupt Pin of CPU
External interrupt 0 External interrupt 1 External interrupt 2 PWM timer Periodic timer 0 Periodic timer 1 INT2 INT3 INT3 INT1 INT0 INT1
Interrupt Source Interrupt Pin of CPU
DMAC GDC PORT TXCAN TXSEI UART INT2 INT2 INT4 INT4 INT4 INT5
4-1
Preliminary
Chapter 4 Interrupt Controller (INTC)
4.2
Registers
Register Overview Name
IRQR IMASKR ILEXT
Phys. Address (hex)
1C04 0000 1C04 0004 1C04 0008
Function
Indicates interrupt sources Enables/ disables interrupts Edge/ level detection of external interrupts
Interrupt Request Register (IRQR), Interrupt Mask Register (IMASKR) IRQR: If an interrupt occurs, the corresponding bit is set to 1. Writing 0 to a bit resets the contents. Writing 1 to a bit does not change the contents. 1 = enables interrupt 0 = disables interrupt (an incoming interrupt will be stored in IRQR, but no interrupt request will be sent to CPU)
30 EXT1 22
(1)
IMASKR:
Bit Name Bit Name Bit Name Bit Name
(1)
31 EXT2 23 MPWM 15 PWM 7 SIO3TX
29 EXT0 21 CAN1EXC 13 SEITX 5 SIO2TX
28 GDC 20 CAN0EXC 12 SEIRX 4 SIO2RX
27 DMAC1 19 SIO3EXC 11 CAN1TX 3 SIO1TX
26 DMAC0 18 SIO2EXC 10 CAN1RX 2 SIO1RX
25 T1 17 SIO1EXC 9 CAN0TX 1 SIO0TX
24 T0 16 SIO0EXC 8 CAN0RX 0 SIO0RX
SEIEXC 14 PORT 6 SIO3RX
Only in IMASKR, in IRQR this bit is wired to zero
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
EXT2 EXT1 EXT0 GDC DMAC1 DMAC0 T1 T0 MPWM SEI EXC CAN1 EXC CAN0 EXC SIO3 EXC SIO2 EXC SIO1 EXC SIO0 EXC External interrupt 2 External interrupt 1 External interrupt 0
Cause of Interrupt
Reset Value
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Vertical or horizontal sync. on GDC DMA on channel 1 finished or error on channel 1 DMA on channel 0 finished or error on channel 0 Periodic timer 1 Periodic timer 0 Overflow on PWM timer enable (only in IMASKR, in IRQR this bit is wired to zero) Exception during TXSEI transfer Status change in TXCAN1 Status change in TXCAN0 Exception during serial I/O on UART channel 3 Exception during serial I/O on UART channel 2 Exception during serial I/O on UART channel 1 Exception during serial I/O on UART channel 0
4-2
Preliminary
Chapter 4 Interrupt Controller (INTC)
Reset Value
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name
PWM PORT SEI TX SEI RX CAN1 TX CAN1 RX CAN0 TX CAN0 RX SIO3 TX SIO3 RX SIO2 TX SIO2 RX SIO1 TX SIO1 RX SIO0 TX SIO0 RX
Cause of Interrupt
PWM counter reached compare value or overflow of PWM counter if enabled by bit 23 of IMASKR Interrupt from PORT module Transmission on TXSEI finished Reception on TXSEI finished Transmission on TXCAN1 finished Reception on TXCAN1 finished Transmission on TXCAN0 finished Reception on TXCAN0 finished Transmission on UART channel 3 finished Reception on UART channel 3 finished Transmission on UART channel 2 finished Reception on UART channel 2 finished Transmission on UART channel 1 finished Reception on UART channel 1 finished Transmission on UART channel 0 finished Reception on UART channel 0 finished
R/W
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
ILEXT The register ILEXT controls edge or level detection of all external interrupt pins. When edge detection is enabled, an interrupt is caused on falling edge. When level detection is enabled, an interrupt is caused on low level. On level detection the bits in IRQR show the current level of the external interrupt pin. Before you can clear the interrupt, the external interrupt signal must be set to 1.
Bit Name 31 30 LEXT2 29 LEXT1 28 LEXT0 27 0
Bit
31 30 29 28 27:0
Name
LEXT2 LEXT1 LEXT0 Wired to zero
Function
Reset Value
0 0 0 0 0
R/W
R R/W R/W R/W R
0 = Edge detection on external interrupt 2 (falling edge) 1 = Level detection on external interrupt 2 (low level) 0 = Edge detection on external interrupt 1 (falling edge) 1 = Level detection on external interrupt 1 (low level) 0 = Edge detection on external interrupt 0 (falling edge) 1 = Level detection on external interrupt 0 (low level) Wired to zero
4-3
Preliminary
Chapter 4 Interrupt Controller (INTC)
4.3
Non Maskable Interrupt
The TMPR3916 generates a non-maskable interrupt exception of the transition from high to low of the NMI* signal. To generate the next non-maskable interrupt exception, the NMI* signal must be set to high again and then to low. The TX39 core completes the current bus operation, before it acknowledges the non-maskable interrupt exception. When the TX39 is not owner of the bus at the moment, the non-maskable interrupt occurs, the non-maskable interrupt must wait until TX39 regains the busmastership.
4-4
Preliminary
Chapter 5 TIMER
5.
TIMER
The TIMER module contains the following features: * * Two periodic timers with variable intervals A PWM timer with variable interval / pulse width (PWM = pulse width modulation)
5.1
PWM Timer
The PWM timer contains a 16 bit counter. The TIMER module sends an interrupt, when the counter reaches a programmable compare value. In addition an interrupt can be sent on the overflow of the counter, if the bit 23 (MPWM) of IMASKR in the Interrupt Controller is set. The PWM counter starts after the bit 15 (PWM) of IMASKR in the Interrupt Controller is set. Setting bit 15 of IMASKR to 0 will clear the PWM Counter.
PWMPre[2:0]
FF /2
FF /4
FF /8
FF / 16
MUX
FF / 32
FF / 64
P CARRY EN CLR
16 Bit Counter
COMPARATOR
T
PWMVAL[15:0] Programmable Register
MPWM
Mask ? &
MPWMCARRY IRQR[15] -> 1
INT[1]
T1 INT
Figure 5.1.1 Block Diagram for Interrupt Generation
5-1
Preliminary
Chapter 5 TIMER
Use the following formula to calculate the time between start of the PWM counter and send of PWM interrupt (pulse width):
PWMVAL = compare value of PWM Timer (see register description of PWMVAL) Time to PWM Interrupt = PWMVAL -----------------------System frequency x 1 / Prescaler
Use the following formula to calculate the time between start and overflow of the PWM counter: Time to PWM Interrupt = 65536 -----------------------System frequency x 1 / Prescaler
Register Overview Name
PWMVAL
Phys. Address (hex)
1C01 0008
Function
Compare value for 16 bit PWM counter
PWM Value Register (PWMVAL)
Bit Name 31 PWMVAL 16 15 3 2 1 PWMPRE 0
Bit
31:16
Name
PWMVAL
Function
Compare Value of PWM Counter If the PWM counter reaches the value of this register an interrupt is generated. Wired to zero Prescaler of PWM Counter The following clock is used to provide PWM counter: 000 = 1/2 system clock 001 = 1/4 system clock 010 = 1/8 system clock 011 = 1/16 system clock 100 = 1/32 system clock 101,110,111 = 1/64 system clock
Reset Value
0x007F
R/W
R/W
15:3 2:0
PWMPRE
0 101
R R/W
5-2
Preliminary
Chapter 5 TIMER
5.2
Periodic Timers
Both periodic timers are running all the time. Every time they reach the end of the interval, they cause an interrupt. The interrupt is maskable in the Interrupt Controller (INTC). Both periodic timers use the same prescaler. Use the following formula to calculate the interval:
T0INT = interval settings of periodic timer 0 (see register description of TITR) T1INT = interval settings of periodic timer 1 (see register description of TITR) Interval of Timer 0 = 2 -----------------------System frequency
(T1INT + 9) (T0INT + 8)
x 1 / Prescaler
Interval of Timer 1
=
2 -----------------------System frequency
x 1 / Prescaler
Note that at the same settings timer 0 has twice the speed of timer 1.
Example:
T0INT = interval setting of Periodic Timer 0 = 010 (bin) = 2 (dec) TPRE = prescaler setting = 100 (bin) Prescaler = 1 / 32 (dec) Interval of Timer 0 = 2 -------------60 MHz
(2 + 8)
x 32
=
32768 -----------60 MHz
= 0.55 msec
Register Overview Name
TIMER TITR
Phys. Address (hex)
1C01 0000 1C01 0004
Function
16 bit free-running counter Settings for periodic timer
TIMER Register (TIMER)
Bit Name 31 TVAL 16 15 0
Bit
31:16
Name
TVAL
Function
Free running counter The free running counter provides the periodic timers. The counter operates continuously on output clock of the prescaler. Write this register only using full word access. Wired to zero
Reset Value
0x0000
R/W
R/W
15:0
-
0x0000
R
5-3
Preliminary
Chapter 5 TIMER
TITR
Bit Name Bit Name 15 31 27 26 25 T1INT 24 23 3 2 19 18 17 T0INT 1 TPRE 0 16
Bit
31:27 26:24 23:19 18:16 15:3 2:0
Name
T1INT T0INT TPRE Wired to zero
Function
Reset Value
0 000 0 000 0 101
R/W
R R/W R R/W R W
Interval of Periodic Timer 1 For interval calculation see above formula Wired to zero Interval of Periodic Timer 0 For interval calculation see above formula Wired to zero Prescaler for Timer 0 and Timer 1 The following clock is used to provide the periodic timer: 000 = 1/2 system clock 001 = 1/4 system clock 010 = 1/8 system clock 011 = 1/16 system clock 100 = 1/32 system clock 101, 110, 111 = 1/64 system clock The prescaler bits read back as zero.
5-4
Preliminary
Chapter 6 Direct Memory Access Controller (DMAC)
6.
Direct Memory Access Controller (DMAC)
The purpose of the Direct Memory Access Controller (DMAC) is to accelerate system speed and to make it easier for software to transfer data between memory and peripheral devices. The DMA Controller contains the following features: * * * * The DMAC consists of two independent channels: channel 0 and channel 1. Channel 0 has higher priority than channel 1 on GBUS transfers. DMA transactions are only possible from device to memory or from memory to device. Devices are for example UART and TXSEI. The DMA transfer will start after request of a peripheral device. That's why only data transfer will happen, when the device needs data. The UARTs, the TXSEI or an external device can send a request. At the end of a transaction or at the occurrence of an error an interrupt will be caused. The interrupt is only maskable in the Interrupt Controller (INTC).
The following sequence shows the principle use of the DMA Controller to transfer data between memory and a peripheral device: 1. 2. 3. 4. 5. 6. Configure the DMA and the peripheral device. Set the number of Bytes to be transferred. The DMA Controller waits for a request of the peripheral device. The DMA Controller transfers data between memory and the peripheral device. The DMA Controller sends an acknowledge to the peripheral device. If there are more bytes left to transfer go to point 2. The DMA Controller causes an interrupt.
6-1
Preliminary
Chapter 6 Direct Memory Access Controller (DMAC)
6.1
Programming the DMA Controller
The programming of both channels are done in the same way. All register values are given in hexadecimal format.
6.1.1
Start DMA Transaction Between Memory and TXSEI/ UART
The DMA transaction between memory and TXSEI/UART is the main application of the DMA Controller. These transactions are only possible as 32-bit word transfers. One data piece fills the lower bits of the memory word. For example: The bytes 0x6E and 0x37 shall be transmitted over the UART. First these bytes have to be stored in bits [7:0] of the words in the memory. The first word in the memory is then 0x0000006E and the second word is 0x00000037. In case of a receive, the data will be stored in the memory in the same way. The rest of the word (higher bits) will be filled with a random value. Execute the following steps to start a DMA transaction: 1. Write the table value in * * bits [3:0] of the Chip Configuration Register (CCR) for channel 0 : bits [7:4] of the Chip Configuration Register (CCR) for channel 1 : Device
SIO 0 SIO 1 SIO 2 SIO 3 TXSEI
Memory >> Device (transmit)
0x0 0x2 0x4 0x6 0x8
Device >> Memory (receive)
0x1 0x3 0x5 0x7 0x9
2.
memory >> device: Write the start pointer of your sending data into the Source Address Register (SAR). Write the address of the device data register into the Destination Address Register (DAR). device >> memory: Write the address of the device data register into the Source Address Register (SAR). Write the start pointer of your receiving data into the Destination Address Register (DAR). Note: You must write the physical addresses into the registers SAR and DAR. All addresses have to be word aligned.
3.
Write the number of bytes you want to transfer into the Byte Count Register (BCR). Note: The DMA Controller transfers a 32-bit word in every step. That's why the byte count must be at least 4. In addition, it must be possible to divide the contents of the Byte Count Register by 4.
6-2
Preliminary
Chapter 6 Direct Memory Access Controller (DMAC)
4. memory >> device: Write the value 0xA9 into the Operation Definition Register (ODR). device >> memory: Write the value 0x69 into the Operation Definition Register (ODR). Write the value 0x11 into the Channel Control Register (CCR). Now the DMA Controller waits for a request of the external device to start the first transfer.
5.
Configure and start the devices TXSEI or UART. After DMA transaction has finished, the DMA Controller sets the OPC bit (bit 0) in the Channel Status Register (CSR) and generates an interrupt. Each channel has its own interrupt signal. The interrupts are only maskable in the Interrupt Controller.
To terminate a running DMA transaction, set bit 22 (ABT) in the Channel Control Register (CCR).
6.1.2
Start DMA with External Device
The TMPR3916 has one pin for an external DMA request signal. For instance the external request makes sense together with a PORT module. The procedure is similar to a UART/ TXSEI transaction. For details of the procedure see section "Start DMA transaction between memory and TXSEI/UART" and the register description. The following steps are executed to start a DMA transaction: 1. Write the hexadecimal-value 0xA in * * 2. 3. 4. bits [3:0] of the Chip Configuration Register (CCR) for channel 0 bits [7:4] of the Chip Configuration Register (CCR) for channel 1
Define source and destination address in registers SAR and DAR. Write the number of bytes you want to transfer into BCR. Write the following value into ODR: Application Memory >> Device (transmit)
0xA8 0xA9
Device >> Memory (receive)
0x68 0x69
Edge detection on external request Level detection on external request
Write the following value into CCR: Application
Positive logic on external request Negative logic on external request
Memory >> Device (transmit)
0x19 0x11
Device >> Memory (receive)
0x19 0x11
Now the DMA Controller waits for a request of the external device to start the first transfer. 5. Configure and start external device. When the DMA Controller starts its first transfer, it sets the external acknowledge signal to 0. After finishing the whole DMA transaction, the DMA Controller sets the external acknowledge signal to 1.
6-3
Preliminary
Chapter 6 Direct Memory Access Controller (DMAC) 6.1.3 Potential Problems
One of the following reasons can be responsible for an error: * * * The software has made invalid settings in the Operation Definition Register (ODR) or in the Channel Control Register (CCR). The software has defined an address in the Source or Destination Address Register (SAR or DAR) that does not exist. The access to this address has caused a bus error. Either the byte count, the source address or the destination address is not correctly aligned. The DMA Controller sends an interrupt, when an error occurs. These steps need to be executed in case of an error: 1. 2. 3. 4. 5. Read the contents of the Channel Error Register (CER) to get the cause of the error. For details see the register description. Write 0x80 into the Channel Control Register (CCR). Write 0x00 into the Channel Status Register (CSR). Start the whole DMA programming procedure from the first point.
6-4
Preliminary
Chapter 6 Direct Memory Access Controller (DMAC)
6.2
Registers
Overview: Register (short name)
ODR0 ODR1 CCR0 CCR1 CER0 CER1 CSR0 CSR1 SAR0 SAR1 DAR0 DAR1 BCR0 BCR1
Physical Address (hex)
1C060000 1C060010 1C060001 1C060011 1C060002 1C060012 1C060003 1C060013 1C060004 1C060014 1C060008 1C060018 1C06000C 1C06001C
Name
Operation Definition Register Channel Control Register Channel Error Register Channel Status Resister Source Address Register Destination Address Register Byte Count Register
Function
Basic channel settings Controls channel operations Cause of an error or interrupt Channel operating status Specifies the address, where to get data from Specifies the address, where to write data to Specifies the number of transfer data in byte units
Operation Definition Register (ODR)
Bit Name 31 SAC 30 DAC 29 PSIZ 28 27 OSIZ 26 25 MSIZ 24 BST
Bit
31
Name
SAC
Function
Specifies, if the Source Address Register should count up. 0 = Source address does not count up (device to memory transfer) 1 = Source address counts up on each transfer (memory to device transfer) This bit should be set to 0, when the DAC bit is set to 1. Specifies, if the Destination Address Register should count up. 0 = Destination address does not count up (memory to device transfer) 1 = Source address counts up on each transfer (device to memory transfer) This bit should be set to 0, when the SAC bit is set to 1. Specifies the size of the device data register. 00 = 8 bits, register bits [31:24] 01 = 16 bits, register bits [31:16] 10 = 32 bits, register bits [31:0] 11 = Setting prohibited Specifies the width of DMA transfer. 00 = 8 bits 01 = 16 bits 10 = 32 bits 11 = Setting prohibited Specifies the bus width of the memory. 0 = 32 bits 1 = 16 bits (there is no use for this setting) Specifies the detection mode for the request signal from the device. 0 = Edge detection 1 = Level detection For UART and TXSEI request signals use level detection.
Reset Value
0
R/W
R/W
30
DAC
0
R/W
29:28
PSIZ
00
R/W
27:26
OSIZ
00
R/W
25
MSIZ
0
R/W
24
BST
0
R/W
6-5
Preliminary
Chapter 6 Direct Memory Access Controller (DMAC)
Channel Control Register (CCR)
Bit Name 23 RST 22 ABT 21 20 CEN 19 RPL 18 17 16 ETE
Bit
23
Name
RST
Function
Performs a software reset on all of the channel registers. 0 = Normal operation 1 = Executes software reset Termination of channel operations regardless of the operating status. 0 = Normal operation 1 = Termination of current DMA transaction Wired to zero. Sets the channel to operating mode. 0 = Channel is inactive 1 = Start DMA transaction Specifies the polarity of the device request signal. 0 = Negative logic (low level / falling edge) 1 = Positive logic (high level / rising edge) UART and TXSEI use negative logic. Wired to zero Decides if the request signal from a device is provided to the DMAC. 0 = No request signal is provided to the DMAC 1 = Request signal is provided to the DMAC Without setting this bit to 1, the DMA controller does not start a transaction.
Reset Value
0
R/W
R/W
22
ABT
0
R/W
21 20
CEN
0 0
R/W R/W
19
RPL
0
R/W
18:17 16
ETE
00 0
R R/W
Channel Error Register (CER)
Bit Name 15 SWA 14 BER 13 ACE 12 CONF 11 SBE 10 DBE 9 BCE 8 AER
Bit
15
Name
SWA
Function
Software Abort: If this bit is set to 1, the software has terminated the current DMA transaction Bus Error: If this bit is set to 1, a bus error has occurred on DMA transfer. Address or Count Error: (ACE = BCE + AER) If this bit is set to 1, a byte count error (BCE, bit 9) or an address boundary error (AER, bit 8) has occurred. Configuration Error: If this bit is set to 1, the software has made invalid settings in the Operation Definition Register (ODR) or in the Channel Control Register (CCR). Bus Error on Source Address Access: If this bit is set to 1, a bus error has occurred during read from a source. Bus Error on Destination Address Access: If this bit is set to 1, a bus error has occurred during write to a destination.
Reset Value
0
R/W
R
14 13
BER ACE
0 0
R R
12
CONF
0
R
11
SBE
0
R
10
DBE
0
R
6-6
Preliminary
Chapter 6 Direct Memory Access Controller (DMAC)
Reset Value
0
Bit
9
Name
BCE
Function
Byte Count Error: If this bit is set to 1, the software has stored a value in the Byte Count Register, which is not correctly aligned. For example: When the DMA Controller transfers 32 bit words, it must be possible to divide the contents of the Byte Count Register by 4. Address Error: If this bit is set to 1, the software has stored a value in the Sourceor Destination Address Register, which is not correctly aligned. For example: When the DMA Controller transfers 32 bit words, the lower two bits of the Source- and the Destination Address Register must be zero.
R/W
R
8
AER
0
R
Channel Status Register (CSR)
Bit Name 7 6 5 4 3 2 ACT 1 EXC 0 OPC
Bit
7:3 2 1
Name
ACT EXC Wired to zero
Function
Reset Value
0 0 0
R/W
R R R/W
Channel Operation Status If this bit is set to 1, the channel is executing a DMA. Exception If this bit is set to 1, an error has occurred during DMA transfer. The cause of error is shown in the Channel Error Register (CER). You can delete the exception by writing 0 to this bit. Writing 1 to this bit shows no effect. Operation Successfully Completed If this bit is set to 1, the DMA transaction has finished without any errors.
0
OPC
1
R
Source Address Register (SAR)
Bit Name 31 SAL 24 23 SAC 0
Bit
31:24 23:0
Name
SAL SAC
Function
Base Address This part of the source address will not count up. Address Offset This part of the source address will count up on every read, when the DMA Controller transfers data from memory to a peripheral device.
Reset Value
0 0
R/W
R/W R/W
6-7
Preliminary
Chapter 6 Direct Memory Access Controller (DMAC)
Destination Address Register (DAR)
Bit Name 31 DAL 24 23 DAC 0
Bit
31:24 23:0
Name
DAL DAC
Function
Base Address This part of the destination address will not count up. Address Offset This part of the destination address will count up on every write, when the DMA Controller transfers data from a peripheral device to the memory.
Reset Value
0 0
R/W
R/W R/W
Byte Count Register (BCR)
Bit Name 31 24 23 BC 0
Bit
31:24 23:0
Name
BC Unused
Function
Reset Value
0 0
R/W
R R/W
These bits contain the number of bytes left to transfer. The DMA Controller decrements the contents of this register after every transfer.
6-8
Preliminary
Chapter 7 CAN Module (TXCAN)
7.
CAN Module (TXCAN)
Outline and Features of TXCAN: * * * * * * * * * * * * * * * * * * * * 2.0 B active Standard identifier and remote frames Extended identifier and remote frames Full-CAN Controller 16 Mailboxes (15 Receive & Transmit + 1 Receive-only) Baud rate up to 1 MBit/sec on the CAN bus at minimum 8 MHz system clock Extended prescaler Bit Timing Parameter like Intel 82527TM selectable mechanism for internal arbitration of transmit messages Time-Stamp for receive and transmit messages Readable Error Counters Warning Level IRQ, Error passive IRQ, Bus-off IRQ Local Loop Back Test Mode (Self Acknowledge) Programmable global mask for mailboxes 0-14 Programmable local mask for mailbox 15 Acceptance mask register for identifier extension bit Flexible interrupt structure Flexible status interface Sleep Mode Wake-up on CAN-bus activity or MCU access
7-1
Preliminary
Chapter 7 CAN Module (TXCAN)
7.1
Block Diagram
TXCAN
Register Bank & Interrupt Logic
Control
Add/ Data
MCU Interface & Access Arbiter
Time Stamp Counter TXCAN State Machine
Mailbox RAM 16* 128
Temporary Transmit Buffer
Temporary Receive Buffer
Acceptance Filter
Clock/ Reset
Reset Controller, Clock & Sleep Logic
CAN Protocol Controller
Rx/Tx
Goes to the whole design
Address / Data Control Signals
Figure 7.1.1 Block Diagram CAN Module
7.1.1
Message Buffers
The message storage is implemented in a single-port RAM, which can be addressed by the inner CAN core and the MCU. The MCU controls the CAN controller by modifying the various mailboxes in the RAM or the configuration registers. In order to initiate a transfer, the transmission request bit has to be set in the corresponding register. Afterwards the entire transmission procedure and possible error handling is done without any MCU involvement. If a mailbox has been configured as receive the MCU reads the mailbox data using MCU read instructions. The mailbox can be configured to interrupt the MCU after every successful message transmission or reception. The mailbox module provides 16 mailboxes of 8-byte data length, 29 bit identifier and several control bits. Each mailbox can be configured as either transmit or receive, except for mailbox 15. This mailbox is a receive-only buffer with a special acceptance mask designed to select groups of message identifiers to be received. The mailbox area is implemented in a single-port-RAM.
7.1.2
Electrical CAN-Interface
The interface to the CAN bus is a simple two-wire line consisting of an input pin Rx and an output pin Tx. The pins are thought to operate with CAN bus transceivers according to ISO/DIS 11989 (e.g. Philips PCA 82C252, Bosch CF150 or Siliconix SI 9200).
7-2
Preliminary
Chapter 7 CAN Module (TXCAN)
7.2
TXCAN Registers
TXCAN Local Memory Map physical base address channel 1 = 1C07 0000 (hex) physical base address channel 2 = 1C07 8000 (hex) Offset Address
0x000 : 0x0F0 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C DPRAM MC MD TRS TRR TA AA RMP RML LAM GAM MCR GSR BCR1 BCR2 GIF GIM MBTIF MBRIF MBIM CDR RFP CEC TSP TSC Mailbox RAM (mailbox 15) Mailbox Configuration Register Mailbox Direction Register Transmit Request Set Register Transmit Request Reset Register Transmission Acknowledge Register Abort Acknowledge Register Receive Message Pending Register Receive Message Lost Register Local Acceptance Mask Register Global Acceptance Mask Register Master Control Register Global Status Register Bit Configuration Register 1 Bit Configuration Register 2 Global Interrupt Flag Register Global Interrupt Mask Register Mailbox Transmit Interrupt Flag Register Mailbox Receive Interrupt Flag Register Mailbox Interrupt Mask Register Change Data Request Remote Frame Pending Register CAN Error Counter Register Time Stamp Counter Prescaler Time Stamp Counter
Name
DPRAM
Description
Mailbox RAM (mailbox 0)
7-3
Preliminary
Chapter 7 CAN Module (TXCAN) 7.2.1 Mailbox Structure
The following picture shows the structure of the mailbox RAM:
Address D7 D3 Mailbox 15 TSV1 ID3 TSV0 ID2 ID1 MCF ID0 0x0F4 0x0F0 D6 D2 D5 D1 D4 D0 0x0FC 0x0F8
D7 D3 Mailbox 0 TSV1 ID3 31
D6 D2 TSV0 ID2 24 23
D5 D1
D4 D0 MCF
0x00C 0x008 0x004 0x000 0
ID1 16 15
Byte 1
ID0 87
Byte 0
Byte 3
Byte 2
Halfword 1 Word
Halfword 0
Figure 7.2.1 Mailbox RAM Structure Each mailbox consists of 16 bytes. The first 4 bytes ID0 to ID3 contain the identifier. Byte 4 (MCF) contains the message control field and byte 5 is unused. Byte 6 and 7 are reserved for the time stamp value TSV of an implemented free running counter that indicates when a message was received or transmitted. The data field consists of the bytes D0 to D7. One mailbox includes the following data: * * * * * * * * 29 bit identifier, 11 bit base ID and 18 bit extended ID (ID0-ID3) identifier extension bit (IDE) (ID3, bit 7) global (local) acceptance mask enable bit GAME (LAME) (ID3, bit 6) remote frame handling bit RFH (ID3, bit 5) remote transmission request bit (RTR) (MCF, bit 4) data length code (DLC) (MCF, bit 0-3) up to eight bytes for the data field (D0-D7) two bytes for the time stamp value (TSV)
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Preliminary
Chapter 7 CAN Module (TXCAN)
Message Identifier (ID0 .. ID3)
Bit Name 31 IDE 30 GAME 29 RFH 28 18 17 ID 0
Bit
31
Name
IDE
Function
Kind of frame (length of identifier) 0 = Standard frames (CAN 2.0A), 11 bit identifier 1 = Extended frames (CAN 2.0B), 29 bit identifier Use of global acceptance mask (mailbox 0 to 14) 0 = The received message will only be stored, when the received identifier is identical to that in the mailbox. 1 = The global acceptance mask will be used for acceptance filtering. The bit 30 of mailbox 15 is called LAME and determines, if the local acceptance mask will be used for acceptance filtering. Always set GAME to "0" for transmit mailboxes. Remote Frame Handling (only for transmit mailboxes) 0 = Software must handle remote frames 1 = The mailbox will automatically respond to remote frames Identifier Contains standard identifier or first bits of extended identifier Identifier Contains the last bits of extended identifier
30
GAME
29
RFH
28:18 17:0
ID ID
Time Stamp Value (TSV)/Message Control Field (MCF)
Bit Name Bit Name 15 31 TSV 5 4 RTR 3 2 DLC 1 0 16
Bit
31:16
Name
TSV
Function
Time-Stamp Counter Value TXCAN contains a 16 bit time-stamp-counter. The value of the time-stamp-counter is stored after the reception and after the transmission of a message. Please refer to chapter "7.2.8 Time Stamp Feature" for a full description of the time-stamp counter's function.
15:5 4
RTR
No function Remote Frame Transmission Request 0 = Normal frame 1 = Remote frame Data Length These bits contain the number of data bytes transferred by the frame. Only the values 0000(bin) to 1000(bin) are allowed. If these bits are set to 1001(bin) or more, the TXCAN will send 8 data bytes.
3:0
DLC
7-5
Preliminary
Chapter 7 CAN Module (TXCAN) 7.2.2 Control Registers
Mailbox Configuration Register (MC)
Bit Name 15 MC 0
Bit
15:0
Name
MC
Function
Mailbox Enable 0 = The corresponding mailbox MBn is disabled for the CAN module and the write access to the identifier field of the mailbox is possible. 1 = The mailbox is enabled for the TXCAN state machine. Write access to the identifier field of an enabled mailbox is denied. Write access to the data field and control field of a mailbox is always possible. After power-up, all bits in MC are cleared and all mailboxes are disabled.
Reset Value
0
Mode
R/W
Special care is required during reprogramming of MC in operation: For a receive mailbox it needs to be ensured that the mailbox is not being disabled while a reception for this mailbox is ongoing. If a mailbox is disabled during an ongoing reception, the user must be aware that the current frame might be received, even though the mailbox has been disabled or reconfigured during the reception of the incoming CAN frame. A transmit mailbox may never be disabled, when a transmit request is pending.
Mailbox Direction Register (MD)
Bit Name 15 MD15 14 MD14 .. MD0 0
Bit
15
Name
MD15
Function
Mailbox Direction of Mailbox 15 Mailbox 15 is receive-only. This bit is always 1 and cannot be changed. Mailbox Direction of Mailboxes 14 to 0 Each mailbox can be configured as transmit mailbox or receive mailbox. 0 = Transmit mailbox 1 = Receive mailbox
Reset Value
1
Mode
R
14:0
MD14 to MD0
0
R/W
The direction of mailboxes may not be changed in operation. A mailbox needs to be disabled before its direction may be changed.
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Preliminary
Chapter 7 CAN Module (TXCAN) 7.2.3 Message Transmission
The transmission control consists of two registers. One register for setting (TRS) and one for resetting (TRR) the transmission request. In this manner it is possible to clear the transmission request without generating a conflict in the handling of the transmit mailboxes in the state-machine. This mechanism also prevents the clearing of the transmission request of a mailbox which transmission is already in progress. The data to be transmitted will be stored in a mailbox configured as transmit mailbox (MDn = 0). After writing the data and the identifier into the mailbox RAM, the message will be sent if the corresponding TRS bit has been set and the mailbox is enabled (MCn = 1). If there is more than one mailbox configured as transmission mailbox and more than one corresponding TRS bit is set, then the messages will be sent in the selected order. The order of transmission can be selected in the Master Control Register (MCR). If MTOS is set to "0", the mailbox with the lower number has the higher priority. For example: if the mailboxes MB0, MB2 and MB5 are configured for transmission and the corresponding TRS bits are set, then the messages will be transmitted in the following order: MB0, MB2 and MB5. If a new transmission request is set for MB0 during the processing of MB2 then in the next internal arbitrationrun MB0 will be selected for the next transmission. This will also happen, when the TXCAN loses arbitration while transmitting MB2. In this case, MB0 will be sent at the next opportunity instead of MB2. If MTOS is set to "1", the priority of the identifier stored in the mailbox will determine the sending order. The mailbox with the higher priority identifier will be sent first. In case of a lost arbitration on the CAN bus line a new internal arbitration run will be started and the message with the highest priority will be sent at the next possible time.
Transmission Request Set Register (TRS)
Bit Name 15 14 TRS 0
Bit
15 14:0
Name
TRS Wired to zero
Function
Reset Value
0 0
Mode
R R/S
Setting TRSn causes the particular message "n" to be transmitted. Several bits can be set simultaneously. The messages will be sent one after the other in the selected transmission order. The transmission order can be selected by the MTOS bit in the Master Control Register (MCR). The bits in TRS will be set by writing "1" at the corresponding bit position from the MCU. Writing a "0" has no effect. After power-up, all bits are cleared.
The TRS bits can only be set by the MCU and will be reset by internal logic in case of a successful transmission or an aborted transmission (if requested by setting the corresponding TRR bit) or a hard/software reset. Bit 15 is not implemented because the mailbox 15 is the receive-only mailbox. If a mailbox is configured as receive the corresponding bit in TRS can not be set by MCU.
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Preliminary
Chapter 7 CAN Module (TXCAN)
Transmission Request Reset Register (TRR)
Bit Name 15 14 TRR 0
Bit
15 14:0
Name
TRR Wired to zero
Function
Reset Value
0 0
Mode
R R/S
Setting TRRn causes a transmission request to be cancelled that was initiated by the corresponding bit TRSn, provided that the transmission of this mailbox is not currently in process. If the corresponding message is currently processed the bit will be reset in the following cases: a successful transmission (normal operation), an aborted transmission in case of a lost arbitration or an error condition detected on the CAN bus line. In case of an aborted transmission, the corresponding status bit AAn will be set and in case of a successful transmission, the status bit TAn will be set. The bits in TRR will be set by writing a "1" from the MCU. Writing a "0" has no effect. After power-up, all bits are cleared.
These bits can only be set by the MCU and reset by the internal logic. They will be reset by internal logic in case of a successful transmission or an aborted transmission. Bit 15 is not implemented because the mailbox 15 is the receive-only mailbox. If TRRn is set the write access to the corresponding mailbox is denied. If a mailbox is configured as receive the corresponding bit in TRR cannot be set by MCU.
Note: When TRSn is set, after setting TRRn to "1": * A transmission request of a message, which is not currently in process, will be cleared immediately (TRSn 0, TRRn 0, AAn 1). * A transmission request of a message which is currently processed will be cleared in case of a lost arbitration or an error condition on the CAN bus (TRSn 0, TRR 0, AAn 1). A transmission request of a message which is currently processed will not be cleared if there is no lost arbitration and no error condition on the CAN bus (TRSn 0, TRRn 0, TAn 1).
*
Transmission Acknowledge Register (TA)
Bit Name 15 14 TA 0
Bit
15 14:0
Name
TA Wired to zero
Function
Reset Value
0 0
Mode
R R/C
If the message of mailbox "n" has been transmitted successfully, the bit "n" of this register will be set and a transmission successful interrupt is generated, if it is enabled. The bits in TA will be reset by writing a "1" from the MCU to TA or TRS. Writing a "0" has no effect. After power-up, all bits are cleared.
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Chapter 7 CAN Module (TXCAN)
Abort Acknowledge Register (AA)
Bit Name 15 14 AA 0
Bit
15 14:0
Name
AA Wired to zero
Function
Reset Value
0 0
Mode
R R/C
If the transmission of the message in mailbox "n" has been aborted, the bit "n" of this register will be set and a transmission abort interrupt is generated, if it is enabled. The bits in AA will be reset by writing a "1" from the MCU to AA or TRS. Writing a "0" has no effect. After power-up, all bits are cleared.
Change Data Request (CDR)
Bit Name 15 14 CDR 0
Bit
15 14:0
Name
CDR Wired to zero
Function
Reset Value
0 0
Mode
R R/W
If the CDR bit of a transmit mailbox is set, a transmission request for this mailbox will be ignored. That means, that a mailbox with TRS and CDR set will not be considered in the internal arbitration-run: the mailbox is locked for transmission. The processing of this mailbox in the arbitration-run will be considered again after clearing the CDR bit. After power-up, all bits are cleared.
CDR is useful for dealing with remote frames. It is intended for updating the data field of a transmit mailbox, which is configured for automatic reply to remote frames (RFH bit set). By using the CDR bit, the user can update the data field without a need of taking additional care of the data consistency. See also section "7.5 Handling of Message-Objects".
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Preliminary
Chapter 7 CAN Module (TXCAN) 7.2.4 Message Reception
The identifier of each incoming message is compared to the identifiers held in the receive mailboxes. The comparison of the identifiers depends on the value of the global/local acceptance mask enable bit (GAME/LAME) stored in the mailbox and the data held in the global/local acceptance mask (GAM/LAM). When a matching identifier is detected, the received identifier, the control bits and the data bytes are written into the matching RAM location. At the same time the corresponding receive message pending bit RMPn is set and a receive-interrupt is generated, if it is enabled. After finding a matching identifier, no further compare will be done. If no match is detected, the message is rejected. The RMP bit has to be reset by the MCU after reading the data. If a second message has been received for this mailbox and the RMP bit is already set, the corresponding message lost bit (RML) is set. In this case, the stored message will be overwritten with the new data. Only if an incoming message does not match to one of the mailboxes 0 to 14, this message will be stored in the receive-only mailbox in case of a matching identifier (acceptance filter). The following figure shows the timing of the flags and the write to the mailbox during message reception:
S O F Message 1 for mailbox "n" E O F I F S S O F Message 2 for mailbox "n" E O F I F S
CAN Bus
Message is valid
Set RMP
RMPn register
Set RML RMLn register Copy ID and data to mailbox
Figure 7.2.2 Timing for Writing Received Message to Mailbox, Including Flags
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Chapter 7 CAN Module (TXCAN)
Receive Message Pending Register (RMP)
Bit Name 15 RMP 0
Bit
15:0
Name
RMP
Function
If mailbox "n" contains a received message, bit RMPn of this register will be set. These bits can only be reset by the MCU, and set by the internal logic. A new incoming message will overwrite the stored one. In this case, the corresponding status bit RMLn will be set before overwriting begins. The bits in RMP and RML can be cleared by a write access to the register RMP with a "1" at the corresponding bit location. After power-up, all bits are cleared.
Reset Value
0
Mode
R/C
Receive Message Lost Register (RML)
Bit Name 15 RML 0
Bit
15:0
Name
RML
Function
If there is an overload condition for mailbox "n", bit RMLn of this register will be set. These bits can only be reset by the MCU, and set by the internal logic. The bits can be cleared by a write access to the register RMP with a "1" at the corresponding bit location. After power-up, all bits are cleared.
Reset Value
0
Mode
R/C
See also section "7.5 Handling of Message-Objects".
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Preliminary
Chapter 7 CAN Module (TXCAN) 7.2.5 Remote Frame Handling
If a remote frame has been received, the internal FSM will compare the identifier to all identifiers of the mailboxes. The comparison of the identifiers depends on the value of the bit global/local acceptance mask enable (GAME/LAME) stored in the mailbox and the data held in the global/local acceptance mask (GAM/LAM). If there is a matching identifier and the RFH bit in this mailbox is set and this mailbox is configured as transmit, this message object will be marked as "to be sent" (TRS will be set). If there is a matching identifier and the mailbox is configured as receive, this message will be handled like a data frame and the corresponding bit in RMP and RFP will be set. After finding a matching identifier, no further compare will be done.
Remote Frame Pending Register (RFP)
Bit Name 15 RFP 0
Bit
15:0
Name
RFP
Function
If a remote frame is received in a mailbox configured as receive mailbox, the corresponding bits in RFPn and RMPn are set. The bits in RFP can be cleared by writing a "1" to the corresponding bit position in RMP. Writing a "0" has no effect. If a remote frame in the mailbox is overwritten by a data frame, the corresponding bit in RFP is cleared. After power-up, all bits are cleared.
Reset Value
0
Mode
R/W
See also section "7.5 Handling of Message-Objects".
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Preliminary
Chapter 7 CAN Module (TXCAN) 7.2.6 Acceptance Filtering
For the mailboxes 0 to 14, the global acceptance mask (GAM) will be used if the bit GAME in the mailbox is set. An incoming message will be stored in the first mailbox with a matching identifier. Only if there is no matching identifier in the mailboxes 0 to 14, the incoming message will be compared to the receive-only mailbox (mailbox 15). If the LAME bit in mailbox 15 is set, the local acceptance mask (LAM) will be used. The acceptance code in the figure below is the content of the identifier words of the current mailbox.
Acceptance Code Register
ACR0 AMR1 RXRqst
Acceptance Mask Register
ACR0 AMR1
AMRn ACRn
Identifier
Figure 7.2.3 Acceptance Filter Logic Local Acceptance Mask (LAM) The local acceptance mask register will only be used for filtering messages for mailbox 15. This feature allows the user to locally mask, or "don't care", any identifier bits of the incoming message for mailbox 15.
Bit Name 31 LAMI 30 29 28 LAM 0
Bit
31
Name
LAMI
Function
0 = The identifier extension bit stored in the mailbox determines which messages shall be received. 1 = Don't care: standard and extended frames can be received. In case of an extended frame all 29 bits of the identifier stored in the mailbox and all 29 bits of the local acceptance mask register will be used for the filter. In case of a standard frame, only the first eleven bits (bit 28 to 18) of the identifier and the local acceptance mask will be used. Wired to zero Incoming messages are first checked for an acceptance match in mailbox 0 to 14 before passing through the mailbox 15. A "1" value means, "don't care" or accept a "0" or "1" for that bit position. A "0" value means that the incoming bit value must match identically to the corresponding bit in the message identifier. The global mask has no effect for mailbox 15. After power-up, all bits are cleared.
Reset Value
0
Mode
R/W
30:29 28:0
LAM
0 0
R R/W
For messages in extended format the identifier extension bit and the whole 29 bits of the identifier will be compared and for messages in standard format only the first 11 bits and the identifier extension bit will be compared. The local acceptance mask will only be used for mailbox 15 (receive-only mailbox).
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Chapter 7 CAN Module (TXCAN)
Global Acceptance Mask (GAM)
Bit Name 31 GAMI 30 29 28 GAM 0
Bit
31
Name
GAMI
Function
0 = The identifier extension bit stored in the mailbox determines which messages shall be received. 1 = Don't care, standard and extended frames can be received. In case of an extended frame all 29 bits of the identifier stored in the mailbox and all 29 bits of the global acceptance mask register will be used for the filter. In case of a standard frame, only the first eleven bits (bit 28 to 18) of the identifier and the global acceptance mask will be used. Wired to zero For each incoming message, the global acceptance mask will be used if the bit GAME is set. A received message will only be stored in the first mailbox with a matching identifier.
Reset Value
0
Mode
R/W
30:29 28:0
GAM
0 0
R R/W
The global acceptance mask will only be used for the mailboxes 0 to 14. After power-up, all bits are cleared.
Master Control Register (MCR)
Bit Name Bit Name 15 7 CCR 14 6 SMR 13 5 TSBTEST 12 4 WUBA 11 SUR 3 MTOS 10 INTLB 2 9 TSTLB 1 TSCC 8 TSTERR 0 SRES
Bit
15:12 11
Name
SUR Wired to zero
Function
Reset Value
0 0
Mode
R R/W
Suspend Mode Request 0 = Normal operation requested 1 = Suspend mode is requested Internal Loop Back Enable 0 = Internal loop back is disabled in test mode 1 = Internal loop back is enabled in test mode Test Loop back 0 = Normal operation requested 1 = Test loop back mode is requested. This mode supports stand-alone operation. Test Error 0 = Normal operation requested 1 = Test error mode is requested. In this mode, it is possible to write the error counters (CEC). Change Configuration Request. 0 = Normal operation requested 1 = Write access to the configuration registers (BCR1 and BCR2) requested. Sleep Mode Request 0 = The sleep mode is not requested (normal operation). 1 = The sleep mode is requested.
10
INTLB
0
R/W
9
TSTLB
0
R/W
8
TSTERR
0
R/W
7
CCR
1
R/W
6
SMR
0
R/W
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Chapter 7 CAN Module (TXCAN)
Reset Value
0 0
Bit
5 4
Name
TSBTEST WUBA
Function
Toshiba Internal Test Mode Always write this register as "0". Wake Up on Bus Activity 0 = The module leaves the sleep mode only by detecting a write access to MCR 1 = The module leaves the sleep mode by detecting any bus activity or by detecting a write access to MCR. Mailbox Transmission Order Select 0 = Mailbox transmission order by mailbox number. The mailbox with the lower number will be sent first. 1 = Mailbox transmission order by identifier priority. The mailbox with the higher priority identifier will be sent first. Wired to zero Time Stamp Counter Clear 0 = No effect 1 = The time stamp counter will be cleared. This bit can only be written and will always be read as zero. Software Reset 0 = No effect 1 = A write access to this register causes a software reset of the module (All parameters will be reset to their initial values). This bit can only be written and will always be read as zero.
Mode
R/W R/W
3
MTOS
0
R/W
2 1
TSCC
0 0
R R/W
0
SRES
0
R/W
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Preliminary
Chapter 7 CAN Module (TXCAN) 7.2.7 Bit Configuration Registers
Bit Configuration Register 1 (BCR1)
Bit Name 15 8 7 BRP 0
Bit
15:8 7:0
Name
BRP Wired to zero
Function
Reset Value
0 0
Mode
R R/W
BRP is the value of the baud rate prescaler.
Bit Configuration Register 2 (BCR2)
Bit Name Bit Name 7 SAM 6 5 TSEG2 15 14 13 4 3 2 TSEG1 1 12 11 10 9 SJW 0 8
Bit
15:10 9:8
Name
SJW Wired to zero
Function
Reset Value
0 0
Mode
R R/W
Indicates by how many units of time-quantums a bit is allowed to be lengthened or shortened when re-synchronising. 00 = 1 time quantum 01 = 2 time quantums 10 = 3 time quantums 11 = 4 time quantums Sample point setting (see below) Timing setting for sampling point (see below) Timing setting for sampling point (see below)
7 6:4 3:0
SAM TSEG2 TSEG1
0 0 0
R/W R/W R/W
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Preliminary
Chapter 7 CAN Module (TXCAN)
The length of a bit is determined by the parameters TSEG1, TSEG2 and BRP. All controllers on the CAN bus must have the same baud rate and bit length. At different clock frequencies of the individual controllers, the baud rate has to be adjusted by the mentioned parameters. In the bit timing logic, the conversion of the parameters to the required bit timing is realized. The configuration registers (BCR1, BCR2) contain the data about the bit timing. Its definition corresponds to the CAN specification 2 (like Intel 82527). The register content is zero after a reset.
Nominal Bit Time SYNCSEG SJW TSEG1 TSEG2 SJW
Transmit Point
Sample Point
Figure 7.2.4 Required Timing Parameters for CAN Transmission The length of TSCL (CAN Bus System Clock) is defined by: TSCL = BRP + 1 fOSC (TQ = time quantum)
1 TSCL = 1 TQ
fOSC is the TXCAN clock frequency (input clock of the TXCAN module). This clock is the output of a prescaler with a divider ratio from 2 up to 8. This ratio can be set in the Chip Configuration Register (CCR). The default setting is 3. The synchronization segment SYNCSEG has always the length of one TSCL. The baud rate is defined by: BR = 1 ((TSEG1 + 1) + (TSEG2 + 1) + 1) TSCL
IPT (information processing time) is the time segment starting with the sample point reserved for processing of the sampled bit level. The information processing time is equal to 3 TXCAN system clock cycles. The parameter SJW (2 bits) indicates, by how many units of TQ a bit is allowed to be lengthened or shortened when re-synchronizing. Values between "1" (SJW = 00b) and "4" (SJW = 11b) are adjustable. The bus line is sampled and a synchronization is performed at each falling edge of the bus signal within a bit grid. With the corresponding bit timing, it is possible to reach a multiple sampling of the bus line at the sample point by setting SAM. The level determined by the CAN bus then corresponds to the result from the majority decision of the last three values. The sample points are at the rising edges of the external SamPoint signal and twice before with a distance of one TXCAN system clock cycle.
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Chapter 7 CAN Module (TXCAN)
This leads to the following restrictions: Restrictions for TSEG2 TQ Length (TXCAN clock cycles)
1 2 BRP+1
BRP
0 1 >1
IPT Length (TXCAN clock cycles)
3 3 3
TSEG2 Minimum Length (in TQ)
3 2 2
Restrictions for TSEG1 The length of TSEG1 should be equal or greater than the length of TSEG2: TSEG1 TSEG2 Restrictions for SJW The maximum length of the synchronization jump width is equal to the length of TSEG2: SJW TSEG2 Restrictions for SAM The three-time sampling is not allowed for BRP<4. For BRP<4 always a one-time sampling will be performed regardless of the value of SAM. Example: A transmission rate of 1 MBit/s will be adjusted, i.e. a bit has a length of 1 s. The clock frequency fOSC is 10 MHz. The baud rate prescaler is set to "0". That means a bit for this data transmission rate has to be programmed with a length of 10*TQ. According to the above formula, the values to be set are always by one smaller than the calculated values. E.g. BRP = 1 (BRP_reg = 0); TSEG1 = 5 (TSEG1_reg = 4), TSEG2 = 4 (TSEG2_reg = 3). With this setting a threefold sampling of the bus is not possible (BRP<4), thus SAM = 0 should be set. SJW is not allowed to be greater than TSEG2, so the maximum value could be set to 4 units (SJW = 3).
7.2.8
Time Stamp Feature
There is a free-running 16-bit timer implemented in the module to get an indication of the time of reception or transmission of messages. The content of the timer is written into the time stamp register of the corresponding mailbox (TSV) when a received message has been stored or a message has been transmitted. The counter is driven from the bit clock of the CAN bus line. When the TXCAN is in configuration mode or in sleep mode, the timer will be stopped. After power-up reset the free running counter can be cleared by writing a value to the time stamp counter prescaler. The counter can be written and read by the MCU in configuration mode and in normal operation mode.
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Chapter 7 CAN Module (TXCAN)
Time Stamp Counter Register
Bit Name 15 TSC 0
Overflow of the counter can be detected by the time stamp counter overflow interrupt flag of the global interrupt flag register GIF and the status flag TSO in GSR. Both flags can be cleared by writing a "1" to the corresponding bit location in GIF. There is a 4-bit prescaler for the time stamp counter. After power-up the time stamp counter is driven directly from the bit clock (TSP = 0). The period TTSC for the time stamp counter will be calculated with the following formula: TTSC = TBIT (TSP + 1) Time Stamp Counter Prescaler Register
Bit Name 15 4 3 2 TSP 1 0
To be sure, that the value of the counter will not change during the write cycle to the mailbox RAM, there is a hold register implemented. The value of the counter will be copied to this register if a message has been received or transmitted successfully. The reception is successful for the receiver, if there is no error until the last but one bit of End-of-frame. The transmission is successful for the transmitter, if there is no error until the last bit of End-of-frame. (Refer to the CAN specification 2.0B) The following figure shows the structure of the time stamp counter:
MCU read/write
Prescaler Register (4 bit)
Re-load value re-load CAN bus bit clock Prescaler (4 bit) clear Count-up clock Free running Time Stamp Counter (16 bit) clear Entering sleep mode Entering configuration mode Write to prescaler Hardware/Software reset
MCU read/write
Hardware/Software reset Entering sleep mode Entering configuration mode Write to prescaler Transmission/Reception successful load Time Stamp Hold Register (16 bit) clear
Mailbox RAM
Figure 7.2.5 Time Stamp Counter
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Chapter 7 CAN Module (TXCAN)
The free running time stamp counter and the time stamp hold register will be cleared in the following cases: * * * * After reset (power-up reset or software reset) When the module enters configuration mode When the module enters sleep mode When a write access to the time stamp prescale register is performed
7.2.9
Status Registers
Global Status Register (GSR)
Bit Name Bit Name 7 CCE 6 SMA 15 14 MsgInSlot 5 4 13 12 11 RM 3 TSO 10 TM 2 BO 9 1 EP 8 SUA 0 EW
Bit
15:12
Name
Msg InSlot
Function
Message In Slot 1111 = No transmit message in slot 0000 = Message 0 is in the transmission slot ... 1110 = Message 14 is in the transmission slot Receive Mode 1 = TXCAN is receiving a message. That means TXCAN is not the transmitter of the message and the bus is not idle. 0 = The CAN module is not receiving a message Transmit Mode 1 = TXCAN is transmitting a message. The module stays transmitter until the bus is idle or it loses arbitration. 0 = The CAN module is not transmitting a message Wired to zero Suspend Mode Acknowledge 1 = TXCAN is in suspend mode 0 = TXCAN is not in suspend mode Change Configuration Enable 1 = The MCU is allowed to do write accesses to the configuration registers. 0 = Write accesses to the configuration registers are denied. Sleep Mode Acknowledge 1 = TXCAN has entered the sleep mode. 0 = Normal operation Wired to zero Wired to zero Time Stamp Overflow Flag 1 = There was at least one overflow of the time stamp counter since this bit has been cleared. To clear this bit, clear the TSOIF bit in the GIF register. 0 = There was no overflow of the time stamp counter
Reset Value
1111
Mode
R
11
RM
0
R
10
TM
0
R
9 8
SUA
0 0
R R
7
CCE
1
R
6
SMA
0
R
5 4 3
TSO
0 0 0
R R R
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Chapter 7 CAN Module (TXCAN)
Reset Value
0
Bit
2
Name
BO
Function
Bus Off status 1 = There is an abnormal rate of occurrences of errors on the CAN bus. This condition occurs when the transmit error counter TEC has reached the limit of 256. During "bus off", no messages can be received or transmitted. The CAN module will go to "bus on" automatically after the "bus off recovery sequence". After entering "bus off", the error counters are undefined. 0 = Normal operation Error Passive status 1 = The CAN module is in the error passive mode. 0 = The CAN module is in the error active mode. Warning status 1 = At least one of the error counters has reached the warning level of 97. 0 = Both values of the error counters are less than 97.
Mode
R
1
EP
0
R
0
EW
0
R
CAN Error Counter Register (CEC)
Bit Name 15 TEC 8 7 REC 0
Bit
15:8 7:0
Name
TEC REC Transmit error counter Receive error counter
Function
Reset Value
0 0
Mode
R R
The CAN module contains two error counters: receive error counter (REC) and transmit error counter (TEC). The values of both counters can be read via the MCU interface. These counters are incremented or decremented according to the CAN specification version 2.0B. A write access to the error counters is only possible in the test error mode (TSTERR bit in MCR is set). In this mode both the TEC and REC counters take over the value written to the lower byte of the register. The receive error counter is not increased after exceeding the error passive limit (128). After the correct reception of a message, the counter is set to a value between 119 and 127 (see CAN specification). After reaching the "bus off" status, the error counters are undefined. If the status "bus off" is reached, the receive error counter is incremented after 11 consecutive recessive bits on the bus. These 11 bits correspond to the gap between two telegrams on the bus. If the counter reaches the count 128, the module changes automatically to the status error active. All internal flags are reset and the error counters are deleted. The configuration registers keep the programmed values. The values of the error counters are undefined during "bus off" status. When TXCAN enters configuration mode (see paragraph "7.4.1 Configuration Mode") the error counters will be cleared.
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Preliminary
Chapter 7 CAN Module (TXCAN)
7.3
TXCAN Interrupt Logic
The TXCAN has the following interrupt sources: * * * * * * * * * * Transmit interrupt: a message has been transmitted successfully Receive interrupt: a message has been received successfully Warning level interrupt: at least one of the two error counters is greater than or equal to 97 Error passive interrupt: TXCAN enters the error passive mode Bus off interrupt: TXCAN enters the bus off mode Time Stamp Overflow Interrupt Transmission abort interrupt Receive message lost interrupt Wake-up interrupt: after wake-up from sleep mode this interrupt will be generated Remote frame pending interrupt
These interrupt sources are divided in three groups: transmit interrupts, receive interrupts and global interrupts. There is one interrupt output line for each group. CANRX is dedicated for receive interrupts, CANTX is dedicated for transmit interrupts and CANEXC for the global interrupts.
Global Interrupt Flag Register (GIF) The interrupt flag bits will be set if the corresponding interrupt condition has occurred. If the corresponding interrupt mask bit is set in the GIM register, the interrupt line IRQ2 will go active high. As long as an interrupt flag in the GIF register is set and the corresponding mask bit is also set, the interrupt line IRQ2 will stay active high ("1").
Bit Name 15 8 7 RFPF 6 WUIF 5 4 3 2 BOIF 1 EPIF 0 WLIF
RMLIF TRMABF TSOIF
Bit
15:8 7
Name
RFPF Wired to zero
Function
Reset Value
0 0
Mode
R R/C
Remote Frame Pending Flag 1 = A remote frame has been received (in a receive-mailbox). This bit will not be set if the identifier of the remote frame matches to a transmit-mailbox with RFH set. 0 = No remote frame has been received. Wake-Up Interrupt Flag 1 = The module has left the sleep mode. 0 = The module is still in sleep mode or normal operation. Receive Message Lost Interrupt Flag 1 = At least for one of the mailboxes, configured as receive, an overload condition has been occurred. 0 = No message has been lost. Transmission Abort Flag 1 = Transmission aborted interrupt-flag. At least one of the bits in the AA register is set. 0 = No transmission has been aborted.
6
WUIF
0
R/C
5
RMLIF
0
R/C
4
TRMABF
0
R/C
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Preliminary
Chapter 7 CAN Module (TXCAN)
Reset Value
0
Bit
3
Name
TSOIF
Function
Time Stamp Counter Overflow Interrupt Flag 1 = There was at least one overflow of the time stamp counter since this bit has been cleared. 0 = There was no overflow of the time stamp counter since this bit has been cleared. Bus Off Interrupt Flag 1 = The CAN has entered the bus off mode. 0 = The CAN module is still in bus on mode. Error Passive Interrupt Flag 1 = The CAN module has entered the error passive mode. 0 = The CAN module is still in error active mode. Warning Level Interrupt Flag 1 = At least one of the error counters has reached the warning level. 0 = None of the error counters has reached the warning level.
Mode
R/C
2
BOIF
0
R/C
1
EPIF
0
R/C
0
WLIF
0
R/C
Note:
All interrupt flags in GIF are independent of the interrupt mask bits. The interrupt flags in GIF can be cleared by writing a "1" to the corresponding bit position. Writing a "0" has no effect.
Global Interrupt Mask Register (GIM)
Bit Name 15 8 7 RFPF 6 WUIF 5 4 3 2 BOIF 1 EPIF 0 WLIF
RMLIF TRMABF TSOIF
The attachment of bits in GIM to the interrupt conditions is equal to that in GIF. Each interrupt flag bit in GIF is masked by the corresponding mask bit in GIM. After power-up, all bits are cleared.
7.3.1
Mailbox Interrupts
There are two separate interrupt output lines for the mailboxes. One interrupt output for mailboxes, which are configured as transmit and one for mailboxes which are configured as receive. There are two interrupt flag registers and one interrupt mask register. One interrupt flag register is for receive mailboxes and one for transmit mailboxes. The interrupt mask register is used for transmit and receive mailboxes. Mailbox Interrupt Mask Register (MBIM) The settings in MBIM determine, for which mailbox the interrupt generation is enabled or disabled. If a bit in MBIM is "0", the interrupt generation for the corresponding mailbox is disabled and if it is "1", the interrupt generation is enabled. Reset value of MBIM is 0.
Bit Name 15 MBIM 0
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Preliminary
Chapter 7 CAN Module (TXCAN)
Mailbox Interrupt Flag Registers (MBTIF/MBRIF)
Bit Name Bit Name 15 15 MBRIF 14 MBTIF 0 0
There are two interrupt flag registers. One for receive mailboxes and one for transmit mailboxes. If a mailbox is configured as receive, the corresponding bits in the transmit interrupt flag register MBTIF will always be read as "0". In MBTIF, bit 15 is not implemented, because mailbox 15 is the receiveonly mailbox. Bit 15 of MBTIF will always be read as "0". If a mailbox is configured as transmit, the corresponding bits in MBRIF will always be read as "0". If a message has been received for mailbox "n" and the mask bit is set to "1" the corresponding interrupt flag "n" of MBRIF will be set to "1" and the interrupt line IRQ0 goes active high ("1"). If a message has been transmitted from mailbox "n" and the mask bit is set to "1" the corresponding interrupt flag "n" of MBTIF will be set to "1" and the interrupt line IRQ1 goes active high ("1"). If the mask bit in MBIM is set to "0", the interrupt flag in MBRIF or MBTIF will not be set and no interrupt will be generated. The information about a successful transmission or reception could be read from the TA or RMP register respectively. The interrupt output lines IRQ0 and IRQ1 will stay at "1" as long as one of the interrupt flags in MBRIF or MBTIF are "1" respectively and the corresponding bits in MBIM are set to "1". The interrupt flags in MBTIF will be cleared by writing a "1" from the MCU to MBTIF and the interrupt flags in MBRIF will be cleared by writing a "1" to MBRIF. Writing a "0" has no effect. The corresponding status flags in TA or RMP have to be cleared separately. After power-up, all interrupt flags are cleared.
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Preliminary
Chapter 7 CAN Module (TXCAN)
7.4
TXCAN Operation Modes
Configuration Mode
The TXCAN has to be initialized before activation. The bit timing parameters can only be modified when the module is in configuration mode. After reset, the configuration mode is active and the CCR bit of MCR and the CCE bit of GSR are set to "1". The TXCAN could be set to normal operation mode by writing a "0" to CCR. After leaving configuration mode, the CCE bit will be set to "0" and the power-up sequence will start. The power-up sequence consists of detecting eleven consecutive recessive bits on the CAN bus line. After the power-up sequence, TXCAN is bus on and ready for operation. To enter configuration mode from normal operation mode the change configuration request bit (CCR) has to be set to "1". After the TXCAN has entered configuration mode, the change configuration enable bit (CCE) will be set to "1". See also the following flowchart. When the TXCAN enters configuration mode the error counters, the time stamp counter and the time stamp hold register will be cleared.
Initialize TXCAN after reset Switch to configuration mode from normal operation mode TXCAN is in normal operation mode: CCR=0 & CCE=0 No Configuration mode requested? Yes No Yes Set CCR to "1" No
7.4.1
TXCAN is in configuration mode: CCR=1 & CCE=1
Set bit timing parameters in BCR1 & BCR2
Normal operation requested? Yes Set CCR to "0" No
CCE = 1 ?
CCE = 0 ? Yes TXCAN is in normal operation mode and starts power-up sequence No 11 consecutive recessive bits detected? Yes TXCAN is bus on and ready for operation
Figure 7.4.1 Configuration Flow Chart for TXCAN
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Preliminary
Chapter 7 CAN Module (TXCAN) 7.4.2 Sleep Mode
The sleep mode will be requested by writing a "1" to SMR (MCR register). When the module enters the sleep mode, the status bit "sleep mode acknowledge" (SMA, GSR register) will be set. During sleep mode, the internal clock of TXCAN is switched off. Only the wake up logic will be active. The read value of the GSR will be f040h, this means, there is no message in slot and the sleep mode is active (SMA is set). Read accesses to all other registers will deliver the value 0000h. Write accesses to all registers but the MCR will be denied. The module leaves the sleep mode if a write access to MCR has been detected or there is any bus activity detected on the CAN bus line (if the wake-up on bus activity is enabled). The automatic "wake up on bus activity" can be enabled/disabled with the configuration bit WUBA in MCR. If there is a write access to MCR or any activity on the CAN bus line (with WUBA = 1), the module begins its power-up sequence. The module waits until detecting 11 consecutive recessive bits on the RX input line, afterwards it goes to bus active. The first message that initiates the bus activity cannot be received. In sleep mode, the CAN error counters and all "transmission requests" (TRS) and "transmission reset requests" (TRR) will be cleared. After leaving the sleep mode, SMR and SMA will be cleared. If the sleep mode is requested while TXCAN is transmitting a message, the module will not switch to the sleep mode immediately. It will continue until a successful transmission or after losing the arbitration, until * * a successful transmission or after loosing the arbitration a successful reception
occurs.
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Preliminary
Chapter 7 CAN Module (TXCAN) 7.4.3 Suspend Mode
The suspend mode will be requested by writing a "1" to SUR (MCR register). When the module enters the suspend mode the status bit SUA (GSR register) will be set to "1". If the CAN bus line is not idle, the current transmission/reception of the message will be finished before the suspend mode will be activated. In suspend mode the TXCAN is not active on the CAN bus line. That means error flags and acknowledge flags will not be sent. The error counters and the error passive flag will not be cleared in the suspend mode. If the suspend mode is requested during the bus off recovery sequence, the module stops after the bus off recovery sequence was finished. The module remains inactive until suspend mode request SUR is deactivated. The suspend mode acknowledge flag is not activated, although the SUR bit is "1" and the module is inactive. To restart the module, the SUR bit has to be programmed to "0". After leaving the bus off state or the inactive state, the module will restart its power-up sequence. TXCAN leaves the suspend mode by writing a "0" to SUR.
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Preliminary
Chapter 7 CAN Module (TXCAN) 7.4.4 Test Loop Back Mode
In this mode TXCAN can receive its own transmitted message and will generate its own acknowledge bit. No other CAN node is necessary for the operation. When the INTLB bit of the MCR register is "0", the internal loop back is disabled. The supposition that TXCAN receives its own messages is that the RX and TX lines must be connected to a CAN bus transceiver or directly together. When the INTLB bit of the MCR register is set to "1", the internal loop back is enabled. In this case, there is no need to connect the RX and TX lines together or to a CAN bus transceiver to make the TXCAN able to receive its own messages. The "test loop back mode" shall only be enabled or disabled when TXCAN is in suspend mode. The following figure shows the set-up procedure. In "test loop back mode" TXCAN can transmit a message from one mailbox and receive it in another mailbox. The set-up for the mailboxes is the same as in normal operation mode.
Enable/disable test loop back mode and/or test error mode TXCAN is in normal operation mode: CCR=0 & CCE=0, SUR=0 & SUA=0 Suspend mode request: set SUR to "1" No
SUA = 1 ?
Yes
Setup TSTLB and/or TSTERR bit: "1" enable, "0" disable Back to normal operation mode with enabled/disabled TSTLB and/or TSTERR: set SUR to "0" No
SUA = 0 ?
Yes End of setup; TXCAN is in normal operation mode with enabled/disabled test loop back and/or test error mode
Figure 7.4.2 Internal Test Flow Chart
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Preliminary
Chapter 7 CAN Module (TXCAN) 7.4.5 Test Error Mode
The error counters can only be written when TXCAN is in test error mode. The "test error mode" shall only be enabled or disabled when TXCAN is in suspend mode. Figure 7.4.2 shows the set-up procedure. When TXCAN is in "test error mode" both error counters will be written at the same time with the same value. The maximum value that can be written into the error counters is 255. Thus, the error counter value of 256 which forces TXCAN into bus off mode can not be written into the error counters.
7.4.6
Special Modes for Dual Channel CAN
* * * Modifications due to adding a second CAN Channel Bits are required from the CCR register. SingleChannelEmu and CanTstInternal. Setting the CanTstInternal to "1" switches to an internal testmode, which is a internal connection independent from any external pins or transceivers.
Internal Test Mode
CHIP Border TXCAN1 & TXCAN2
RXCAN1 RXCAN2
Figure 7.4.3 Internal Test Mode *
The Signal "SingleChannelEmu" connects 2 channels to be able to work on only 1 transceiver.
Single Transceiver Mode
CHIP Border TXCAN1 & TXCAN2 Transceiver RXCAN1 RX RXCAN2 TX
Figure 7.4.4 Single Transceiver Mode The following table shows the bit function of CANM in the Chip Configuration Register (CCR): CANM
00 X1 10
CAN Mode
Normal operation Internal Test mode 1 Transceiver - Mode
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Chapter 7 CAN Module (TXCAN)
7.5
Handling of Message-Objects
In the following sections, there are suggestions how to handle message objects.
7.5.1
Receiving Messages
The following flowchart shows the handling of receive objects using receive interrupt IRQ0.
Setup a mailbox for message reception
Receiving messages
Disable mailbox: set MCn to '0'
Yes
New setup for the mailbox?
No
Configure mailbox for reception: set MDn to '1'
Wait for IRQ0
No
Yes
Setup mailbox identifier and IDE bit for standard or extended ID
Check RMP or MBRIF to determine the mailbox with RMP set
Clear MBRIF and return from interrupt service routine
Set LAME / GAME of the mailbox if necessary
Read out the mailbox
Special user tasks ...
Setup LAM / GAM if necessary
Clear RMPn, this clears also RML
RMLn = 1 ? Enable interrupts: set MBIMn to '1'
No
Yes Enable mailbox: set MCn to '1'
Yes, Data has become inconsistent reading it out!
Clear RMPn, this clears also RML No End of setup Read Out Mailbox again
RMPn = 1 ?
Figure 7.5.1 Receiving Objects Using IRQ0 It is also possible to use polling. In this case, the "waiting for IRQ0" in above flowchart must be replaced by polling RMP. Enabling interrupts and clearing MBRIF must be removed from the flow.
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Preliminary
Chapter 7 CAN Module (TXCAN) 7.5.2 Transmitting Messages
The following flowchart shows the handling of transmit objects by using the transmit interrupt IRQ1. It is also possible to use polling. In this case, the "waiting for IRQ1" in the flowchart must be replaced by polling TA. Enabling interrupts and clearing MBTIF must be removed from the flow.
Setup a mailbox for message transmission
Transmitting messages
Disable mailbox: set MCn to "0"
Yes
New setup for the mailbox?
No
Configure mailbox for transmission: set MDn to "0"
Update mailbox data?
Yes Setup mailbox identifier and IDE bit for standard or extended ID
No
Write new data to the mailbox
No Choose transmission order: setup MTOS
Transmission requested?
Enable interrupts: set MBIMn to "1"
Yes
Enable mailbox: set MCn to "1"
Set transmission request: set TRSn to "1"
No
End of setup Wait for IRQ1
Yes
Check TA to determine the mailbox with TA set
Special user tasks ... (Update mailbox data?)
Clear TA and MBTIF and return from interrupt service routine
Figure 7.5.2 Transmitting Objects Using IRQ1
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Preliminary
Chapter 7 CAN Module (TXCAN) 7.5.3 Remote Frame Handling
The following flowchart shows the handling of remote frames by using the automatic reply feature. This feature is available when the RFH bit of a mailbox, which is configured for transmission, is set. To avoid data inconsistency problems when updating the mailbox data the CDR register is used.
Setup a mailbox for automatic reply to remote frames
Automatic reply to remote frames
Disable mailbox: set MCn to '0'
Yes
New setup for the mailbox?
No
Configure mailbox for transmission: set MDn to '0'
Update mailbox data?
No
Yes Setup mailbox identifier and IDE bit for standard or extended ID
Change data requested: set CDRn to '1'
Set RFH bit of the mailbox; set GAME if necessary
Write new data to the mailbox
Setup GAM if necessary
Reset CDRn: set CDRn to '0'
Choose transmission Order: setup MTOS
Enable mailbox: set MCn to '1'
End of setup
Figure 7.5.3 Automatic Reply Generation for Remote Frames
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Preliminary
Chapter 8 Parallel Interface (PORT)
8.
Parallel Interface (PORT)
The PORT-module is a general-purpose parallel interface. The PORT-Module contains the following features: * * * 30 pins each pin can be configured independently as input or output each pin can generate an interrupt on rising or falling edge of input-signal The PORT module shares its pins with modules GDC, TXSEI and UART. Bit assignment of all PORT registers:
Bit Pin Access Bit Pin Access Bit Pin Access Bit Pin Access 23 PIO23 R/W 15 PIO15 R/W 7 PIO7 R/W 31 RO 22 PIO22 R/W 14 PIO14 R/W 6 PIO6 R/W 30 29 PIO29 R/W 21 PIO21 R/W 13 PIO13 R/W 5 PIO5 R/W 28 PIO28 R/W 20 PIO20 R/W 12 PIO12 R/W 4 PIO4 R/W 27 PIO27 R/W 19 PIO19 R/W 11 PIO11 R/W 3 PIO3 R/W 26 PIO26 R/W 18 PIO18 R/W 10 PIO10 R/W 2 PIO2 R/W 25 PIO25 R/W 17 PIO17 R/W 9 PIO9 R/W 1 PIO1 R/W 24 PIO24 R/W 16 PIO16 R/W 8 PIO8 R/W 0 PIO0 R/W
wired to zero
Register Function: Each bit of the following registers is assigned to the corresponding pin. The table below describes the function of each register for one pin. Physical Address (hex)
1C03 0014
Register
PAMUX
Function of One Bit
Determines which module uses the pin. Each bit in this register represents the setting of one PIO. The upper both bits (31 and 30) are not relevant, because the TMPR3916F provides 30 PIOs. 0 = PORT module uses the pin 1 = GDC, TXSEI or UART (depending on the pin) Further descriptions see section "Pin Assignment" on next side. This register contains data read from PORT pins or written to PORT pins. When a pin is used as input, then the corresponding bit in this register is read only. Direction of pin 0 = Input 1 = Output The contents of this bit shows no effect, when PAMUX = 1. Interrupt enable 0 = Disable interrupt 1 = Enable interrupt Whether the interrupt caused on falling or rising edge of input signal, depends on the contents of PALMX register. When the pin is used by another resource or the pin is used as output, the interrupt is inhibited.
Reset Value
0
PA
1C03 0000
0
PACR
1C03 0004
0
PAMSK
1C03 0010
0
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Preliminary
Chapter 8 Parallel Interface (PORT)
Physical Address (hex)
1C03 000C
Register
PALMX
Function of One Bit
Controls edge detection for interrupt generation 0 = Cause an interrupt on falling edge 1 = Cause an interrupt on rising edge The contents of this register show no effect, if PAMSK is set to 0. Interrupt flag 0 = No interrupt has occurred on pin 1 = Interrupt has occurred on pin Bits in this register are set, when a rising edge or a falling edge (depending on PALMX setting) on the corresponding PIO pin is detected and the PIO was enabled for interrupts (PAMSK). Flags are only set if the PIO is configured to be an input (PACR) and is used by the PORT module (PAMUX). Each flag can be reset to 0 by writing a 0 to it. Before you can reset a PORT-interrupt in the interrupt controller, you must reset the interrupt flag in PAL register. Writing 1 to this register has no effect.
Reset Value
0
PAL
1C03 0008
0
Pin Assignment The PAMUX register in the PORT module and the SEIMUX bits in the Chip Configuration Register (CCR) determine the use of the PIO pins. The following table shows the pin use and the corresponding bit settings: Register Settings
PAMUX = 0 PAMUX = 1 and SEIMUX = 0 PAMUX = 1 and SEIMUX = 1
PIO0 .. PIO15
PORT GDC GDC
PIO16 .. PIO29
PORT UART TXSEI
Example for register configuration: Task
pins 0 to 15 are used by GDC, pins 16 to 29 are used by PORT pins 16 to 20 are used as outputs, pins 21 to 29 are used as inputs following pins should cause an interrupt - a signal change from low to high on pin 24 - a signal change from high to low on pin 25 => =>
Solution
PAMUX = 0x0000FFFF PACR = 0x000F0000 PAMSK = 0x03000000 PALMX = 0x01000000
=>
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Preliminary
Chapter 9 Synchronous Serial I/O (TXSEI)
9.
Synchronous Serial I/O (TXSEI)
The Toshiba TX Serial Expansion Interface is a synchronous communication unit and compatible to peripheral devices, which can be connected to an SPI/SEI type interface. TXSEI's flexible clock control logic allows the selection of clock polarity and phase for the transfer protocol. When TXSEI is configured as a master, a large number of different bit rates with up to 15 MHz clock rate in the master mode can be selected. In slave mode transmissions up to 7.25 MHz are possible (assuming the TMPR3916 is operating with 60 MHz) The built-in error detection logic allows the detection of various error situations, which can occur during SEI transfers. TXSEI also offers DMA support for automated data transfers to its shift registers. By the use of DMA a larger number of transfers can be scheduled at once. In particular, the usage of DMA allows a more cost-effective implementation than usual large queue or buffer structures. TXSEI is able to perform seamless transfers of consecutive frames. Alternatively, the minimum delay between two consecutive transfers is programmable for master mode. Feature Overview: * * * * * * * * * * * * * Phase and Polarity Selection Transfer sizes of 5 to 16 bits DMA operation: Full-Duplex 2 channels, Half-Duplex 1 channel Built-in Error Detection Logic 4 frame transmit, 4 frame receive buffers Compatible with SPI type interfaces Master and Slave operation 15 Mbps data-rate when operated with 60 MHz clock rate. Inter Frame Space Delay Feature seamless transfer of large values without delay between consecutive frames integrated MSB / LSB first reordering Stop and Flush Buffer functionality for fast event response programmable buffer-fill-level dependent receive / transmit interrupts
9-1
Preliminary
Chapter 9 Synchronous Serial I/O (TXSEI)
9.1
TXSEI Structure
The following figure roughly shows the internal structure of the TXSEI and the connectivity to the outside of the chip via the PORT-Multiplexer:
Connection to internal system bus
MCU Interface & Configuration Registers
P o r t c o n t r o l Output enables
Control logic
Tx-FIFO
Rx-FIFO
Shift-Register
PORT-Muliplexer PIOs 16,17,18,19, 22
CLK
RX(SEI)
TX(SEI)
SSO
SSI
IO-directions dependent on mode (slave/master)
SEIMUX
Chip Configuration R.
Figure 9.1.1 Internal Structure of TXSEI
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Preliminary
Chapter 9 Synchronous Serial I/O (TXSEI)
9.2
Registers
The following table shows a map of the TXSEI I/O-Space: Register (short name)
SEMCR SECR0 SECR1 SEFS SESS SESR SEDR SERS
Physical Address (hex)
1C00 8000 1C00 8004 1C00 8008 1C00 800C 1C00 8010 1C00 8014 1C00 8018 1C00 801C
Name
Master Control Register SEI Control Register 0 SEI Control Register 1 SEI Inter Frame Space Register SEI Slave Select Space Register SEI Status Register SEI Data Register SEI Read Start Register
Function
Mode settings General settings Definition of bit-rate and transfer-size Definition of space between frames Slave select timer settings Status information Transmit and receive data Alternative register to read received data
TXSEI's registers can be accessed using Byte, Half-Word and Word instructions. Bits [31:16] are unused in all registers. These bits are wired to zero and read-only.
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Preliminary
Chapter 9 Synchronous Serial I/O (TXSEI)
SEI Master Control Register (SEMCR)
Bit Name Bit Name Bit Name Bit Name 7 OPMODE 6 5 4 15 14 13 12 3 2 LOOP 1 SESTP 0 BCLR 23 22 21 20 11 10 9 8 31 30 29 28 19 18 17 16 27 26 25 24
Bit
31:8 7:6
Name
OPMODE Unused
Function
Reset Value
0x000000 01
R/W
R R/W
Operation Mode 00 = Don't care. Writing this value to the OPMODE bits doesn't change anything 01 = Configuration Mode: Use this mode to change the settings of the bits MSTR, SBOS, SPOL and SPHA in SECR0 and also the SECR1 register. 10 = Active Mode: normal operation mode 11 = Reserved. Do not use this setting In Configuration Mode the SESTP and LOOP bit and also the receive and transmit FIFO will be cleared. The master and slave control modules will be kept in reset. Running transfers are immediately aborted, even within the current frame. Wired to zero Loop Enable: If TXSEI is configured as a Master, this bit can be used to switch a loop-back from the TX to the RX pin for diagnostic purpose. It could be set only when the TXSEI is in active mode and configured as a master. Setting the TXSEI in configuration mode will clear this bit. 0 = Loop disabled, normal operation 1 = Loop enabled SEI Stop This bit is used only during master mode. If this flag is asserted, the module will stop the transfer after the current frame has been completed. This bit could be set only when the TXSEI is in active mode and configured as a master. Setting the TXSEI in configuration mode will clear this bit. 0 = Normal operation 1 = Module will stop after completion of the current transfer SEI Buffer Clear This flag is used to clear the receive and transmit FIFO and can only be used in master mode. The internal buffers can only be cleared, if the module is already in stop mode. In this case, the FIFO logic can be reset by writing a "1" value to this bit. The module can be taken out of the stop mode in the same access. A stop of TXSEI and clearance of the buffers might become necessary to guarantee a fast response to events. It is recommended to wait until the TXSEI module is idle (SIDLE=1) before activating BCLR. This bit will always be read as "0".
5:3 2
LOOP
000 0
R R/W
1
SESTP
0
R/W
0
BCLR
0
R/W
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Chapter 9 Synchronous Serial I/O (TXSEI)
SEI Control Register 0 (SECR0)
Bit Name Bit Name Bit Name Bit Name 7 15 TXIFL 6 5 SSIVAL 14 13 RXIFL 4 IFSPSE 12 23 22 21 20 11 SILIE 3 MSTR 10 SOEIE 2 SBOS 9 SUEIE 1 SPHA 8 STFIE 0 SPOL 31 30 29 28 19 18 17 16 27 26 25 24
Bit
31:16 15:14
Name
TXIFL Unused
Function
Reset Value
0x0000 00
R/W
R R/W
Transmit Interrupt Fill Level (SEITX): 00 = Interrupt, if one or more Tx values can be stored 01 = Interrupt, if two or more Tx values can be stored 10 = Interrupt, if three or more Tx values can be stored 11 = Interrupt, if four or more Tx values can be stored The first setting (TXIFL = 00) should be used, if the DMA Controller is used for transferring values for TXSEI transmissions. Receive Interrupt Fill Level (SEIRX): 00 = Interrupt, if one or more Rx values are stored 01 = Interrupt, if two or more Rx values are stored 10 = Interrupt, if three or more Rx values are stored 11 = Interrupt, if four or more Rx values are stored The first setting (RXIFL = 00) should be used, if the DMA Controller is used for transferring values from TXSEI receptions. SEI IDLE Interrupt Enable: 0 = Disable SIDLE as an interrupt source for SEIEXC 1 = Enable SIDLE as an interrupt source for SEIEXC SEI Overflow Error Interrupt Enable: 0 = Disable SEOE as an interrupt source for SEIEXC 1 = Enables SEOE as an interrupt source for SEIEXC SEI Underflow Error Interrupt Enable: 0 = Disable SEUE as an interrupt source for SEIEXC 1 = Enables SEUE as an interrupt source for SEIEXC SEI Transfer Format Error Interrupt Enable: 0 = Disable SETF as an interrupt source for SEIEXC 1 = Enable SETF as an interrupt source for SEIEXC Wired to zero SSI valid Determines if the Slave Select input signal is valid in master mode or not. If valid, the SSI signal will be observed in master mode to generate a transfer format error. 0 = SSI not valid in master mode 1 = SSI valid in master mode Inter Frame Space Prescaler Enable (valid only in master mode). 0 = IFS prescaler disabled 1 = IFS prescaler enabled Master / Slave Mode Select 0 = TXSEI is configured as slave 1 = TXSEI is configured as master
13:12
RXIFL
00
R/W
11
SILIE
0
R/W
10
SOEIE
0
R/W
9
SUEIE
0
R/W
8
STFIE
0
R/W
7:6 5
SSIVAL
0 0
R R/W
4
IFSPSE
0
R/W
3
MSTR
0
R/W
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Preliminary
Chapter 9 Synchronous Serial I/O (TXSEI)
Bit
2
Name
SBOS
Function
SEI Bit Order Select 0 = LSB first operation, the least significant bit is shifted first 1 = MSB first operation, the most significant bit is shifted first SEI Phase This flag selects one of two fundamentally different transfer formats. 0 = Sample on 1st edge, Shift on 2nd edge 1 = Shift on 1st edge, Sample on 2nd edge. SEI Polarity 0 = Active High Clocks selected; SCLK idles low 1 = Active Low Clocks selected; SCLK idles high
Reset Value
0
R/W
R/W
1
SPHA
0
R/W
0
SPOL
0
R/W
Note: Bits 0 to 5 of this register can only be changed in configuration mode.
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Chapter 9 Synchronous Serial I/O (TXSEI)
SEI Control Register 1 (SECR1) The number of bits per frame is configured using this register. This register could only be written, when the module is in configuration mode.
Bit Name Bit Name Bit Name Bit Name 7 6 5 4 15 14 13 12 SER 3 2 SSZ 1 0 23 22 21 20 11 10 9 8 31 30 29 28 19 18 17 16 27 26 25 24
Bit
31:16 15:8
Name
SER Unused
Function
Reset Value
0x0000 0x01
R/W
R R/W
In master-mode, this setting controls the bit-rate for transmission. The internal clock rate generator is implemented as a down counter. The SER setting specifies the reload value for this counter. wired to zero Transfer Size 0x05 = 5 bits 0x06 = 6 bits ... ... 0x10 = 16 bits others = invalid setting Note: If SSZ has an invalid setting, the TXSEI will not work properly.
7:5 4:0
SSZ
0 0
R R/W
This register can only be written, if TXSEI is in configuration mode. The clock-rate on the SEI bus can be calculated using the following formula: fSEI = fsystem 2 (SER + 1)
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As an example, some common settings for fSYS = 60 MHz are shown in the table below: Sustained Peak Data Rate half-duplex
0x00 0x01 0x02 0x03 0x04 0x05 0x09 0x13 0xFF Invalid setting 15 MHz 10 MHz 7.5 MHz 6 MHz 5 MHz 3 MHz 1.5 MHz 117.1875 kHz Invalid setting 15 Mbps 10 Mbps 7.5 Mbps 6 Mbps 5 Mbps 3 Mbps 1.5 Mbps 117.1875 kbps
SER Setting
SEI Clock Rate (fSEI)
Sustained Peak Data Rate full-duplex
Invalid setting 30 Mbps 20 Mbps 15 Mbps 12 Mbps 10 Mbps 6 Mbps 3 Mbps 234.375 kbps
In slave mode, the setting is ignored and the clock is derived from the clock on the SEI bus. Note: Due to the internal over-sampling, if the module is operated in slave mode, the input baud-rate must be slightly less than 1/8 of the input system clock to the module. (e.g. 60 MHz system input clock => SPI slave baud rate max. 7.25 Mbps)
SEI Inter Frame Space Register (SEFS)
Bit Name Bit Name Bit Name Bit Name 7 6 5 15 14 13 4 IFS[7:0] 3 2 1 12 23 22 21 20 11 10 9 IFS[9:8] 0 8 31 30 29 28 19 18 17 16 27 26 25 24
Bit
31:10 9:0
Name
IFS Unused
Function
Reset Value
0x000000 0
R/W
R R/W
Inter frame space: Time between two consecutive transmission frames
This register is used to configure the amount of time, which is inserted between two consecutive frames. The time is guaranteed by an internal 10-bit down counter. The counter can be operated with or without prescaler. The IFSPSE bit of the SECR0 register determines whether the prescaler should be used or not. When operating without prescaler, the counter runs on SEI system clock. When operating with prescaler, the counter runs on 1/32 of SEI system clock.
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Preliminary
Chapter 9 Synchronous Serial I/O (TXSEI)
This counter is implemented as a down counter. It is reloaded each time a transfer is completed. When another transfer is buffered, the new transfer value will be loaded to the shift buffer after the timer has expired and the transmission will start. The Inter Frame Space Timer can be disabled by setting this register to "0" and two consecutive transfers will be sent using only the minimum amount of time required to load the buffers between consecutive frames (seamless transfer). When the counter reload value in the IFS register is "0" the inter frame space will be one system clock cycle (16.67 ns at 60 MHz system clock). When the prescaler is not used, the inter frame space can be calculated using the following formula: t IFS = IFS + 1 fSYS (range: 16.67 ns up to 17.07 s at 60 MHz system clock)
When using the prescaler, the inter frame space can be calculated using the following formula: t IFS = 32 x(IFS + 1) fSYS (range: 533.33 ns up to 546.13 s at 60 MHz system clock)
The IFS register can be written in configuration mode and in active mode. Writing to the IFS register always clears the Inter Frame Space counter. Therefore, if the shift buffer contains a message, which is waiting to be transferred, this message will be sent immediately, as soon as the IFS register is being written. This will also be the case, if the old value is rewritten to the register. If this behavior is not intended, it is possible to wait for SIDLE flag becoming "0", before writing to the register. The IFSD flag in the SESR register is asserted for the time the transfer is delayed by the IFS mechanism.
SEI Slave Select Space Register (SESS)
Bit Name Bit Name Bit Name Bit Name 7 6 5 4 SESS 15 14 13 12 3 2 1 0 23 22 21 20 11 10 9 8 31 30 29 28 19 18 17 16 27 26 25 24
Bit
31:8 7:0
Name
SESS Unused
Function
Reset Value
0x000000 0
R/W
R R/W
Slave Select Space: Time between assertion of slave select signal and transmission start
The contents of this register is the reload value of the Slave Select Timer. Write accesses to this register are possible in configuration mode and in active mode. Writing to this register clears the slave select counter. This register is used to configure the amount of time, which is inserted between activating the slave select output signal in master mode and starting the transfer and between the transfer end and deactivating the slave select output signal. The time is guaranteed by an internal 8-bit down counter. The counter runs on SEI
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Chapter 9 Synchronous Serial I/O (TXSEI)
system clock. When writing to the SESS register while the shift buffer contains a message, which is waiting to be transferred, this message will be sent immediately, since the counter is cleared to "0". The slave select space can be calculated using the following formula: Pre-transfer time: tSSC_PRE = 2 + SESS fSYS (range: 33.33 ns up to 4.28 s at 60 MHz system clock)
Post-transfer time: tSSC_POST = 3 + SESS fSYS (range: 50 ns up to 4.3 s at 60 MHz system clock)
The Slave Select Space Timer can be disabled by setting this register to "0". The minimum time between setting the slave select signal and starting the transfer is 2 system clock cycles and the minimum time between the transfer end and deactivating the slave select signal is 3 system clock cycles. This is the case when SESS is set to "0". The minimum time between two consecutive transfers is the sum of the minimum values of tSCC_PRE, tIFS and tSCC_POST: this is 6 system clock cycles.
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Chapter 9 Synchronous Serial I/O (TXSEI)
SEI Status Register (SESR) In the SEI Status Register, the status flags can only be read, while error flags are cleared by writing a "1" value to the respective bit position. Writing a "0" to the Error Flags has no effect.
Bit Name Bit Name Bit Name Bit Name 15 TBSI 7 SEOE 14 RBSI 6 SEUE 5 SETF 13 12 TBS 4 3 IFSD 2 SIDLE 23 22 21 20 11 10 9 RBS 1 STRDY 0 SRRDY 8 31 30 29 28 19 18 17 16 27 26 25 24
Bit
31:16 15 14 13:11
Name
TBSI RBSI TBS Unused
Function
Reset Value
0x0000 1 0 000
R/W
R R R R
Transmit Buffer Status Indicator This register indicates a transmit fill level interrupt Receive Buffer Status Indicator This register indicates a receive fill level interrupt Transmit Buffer Status This register shows the status of the transmit buffer. 000 = Transmit Buffer Empty 001 = 1 transfer stored 010 = 2 transfers stored 011 = 3 transfers stored 100 = 4 transfers stored, Buffer full Receive Buffer Status This register shows the status of the receive buffer. 000 = Receive Buffer Empty 001 = 1 transfer stored 010 = 2 transfers stored 011 = 3 transfers stored 100 = 4 transfers stored, Buffer full SEI Overflow Error: This flag indicates that a value in the receive buffer has been overwritten, before it could be read. This flag always reads "0" in master mode. In slave mode, it can be cleared by writing a "1" value to it. This flag will be cleared by setting the module in configuration mode. SEI Underflow Error: This flag indicates that an external master tried to shift the shift register, while no new output values were specified by writing to the data register. This flag always reads "0" in master mode. In slave mode it is cleared by writing a "1" to it. This flag will be cleared by setting the module in configuration mode. SEI Transfer Format Error: This flag indicates a violation of the transfer format. See paragraph "Transfer Format Error". It can be cleared by writing a "1" to it. This flag will be cleared by setting the module in configuration mode. Unused
10:8
RBS
000
R
7
SEOE
0
R/C
6
SEUE
0
R/C
5
SETF
0
R/C
4
0
R
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Chapter 9 Synchronous Serial I/O (TXSEI)
Reset Value
0
Bit
3
Name
IFSD
Function
SEI Inter Frame Space Delay Indicator: This Flag is asserted during the time, where one frame has been processed and the next frame is being delayed by the inter-framespace timer. SEI Idle Indicator: This flag is asserted, if no transfer is in progress and if the transmit buffer is empty or the stop mode (SESTP=1) is activated in master mode. SEI Transmit Ready: This flag indicates, that the transmit buffer is ready to receive new data. The flag is cleared, if the transmit buffer is full. SEI Receive Ready: This flag indicates, that there is valid data stored in the receive buffer. This flag is cleared when emptying the receive buffer while reading SEDR or SERS register
R/W
R
2
SIDLE
1
R
1
STRDY
1
R
0
SRRDY
0
R
SEI Data Register (SEDR)
Bit Name Bit Name Bit Name Bit Name 7 DR[7:0] 15 14 13 12 DR[15:8] 0 23 22 21 20 11 10 9 8 31 30 29 28 19 18 17 16 27 26 25 24
Bit
31:16 15:0
Name
DR Unused
Function
Reset Value
0x0000 0
R/W
R R/W
Data register for transmission and reception
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Chapter 9 Synchronous Serial I/O (TXSEI)
MCU Bus Other registers SERS read & start read Receive Buffer SEDR write Transmit Buffer
Shift Buffer
IN
CLK
OUT
Figure 9.2.1 Data Paths in TXSEI The actual shift register is buffered for both transmission and reception. The receive and transmit buffers are implemented as FIFO with a depth of four frames. A write to SEDR register writes the value to the transmit buffer. From there, the data will be transferred to the shift register as soon as TXSEI is ready for the next transfer. Reading the SEDR register delivers the current value from the receive FIFO and increments the receive FIFO pointer, if there are other values stored in the FIFO. The shift-buffer is the physical register, which is used during SEI transfers for shifting in/out the data. Besides SEDR, the SERS register offers a second method to access the transfer values. Data in both the SEDR and the SERS register are stored right aligned. E.g.: For eight bit transfers, only the lower eight bits of the SEDR register are used. For 16 bit transfers the lower 16 bits of SEDR are used. When reading this register, unused bits, except the upper 16 bits, are undefined. The upper 16 bits always read to zero.
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Chapter 9 Synchronous Serial I/O (TXSEI)
SEI Read Start Register (SERS)
Bit Name 31 30 29 28 27 26 25 24
Bit Name Bit Name Bit Name
23
22
21
20
19
18
17
16
15 RS[15:8] 7 RS[7:0]
8
0
Bit
31:16 15:0
Name
RS Unused
Function
Reset Value
0x0000 0
R/W
R R/W
Read Start: Reads received data and immediately starts a transmission.
The SERS register offers a second method to fetch values from the receive buffer. Reading this register returns the value from the receive buffer. Just like a read from the data register would. In contrast to reading the data register, the read from the SERS register counts for two register accesses: a read from the data register and a write of value 0xFFFF to the data register. Therefore, in master mode a read access to this register will not only return the value from the receive buffer, but will also start a new transfer. In slave mode, the received data will be delivered and the data 0xFFFF will be written to the data register, but the transfer will start when the master activates the slave select signal and switches on the SCLK clock. In order not to have TX buffer underruns the user should initially write some data via the SEDR into the TX buffer. The register is useful during half-duplex operations, where data is read from SPI, while "don't care data" is shifted out. It can be specified as DMA source address to save a valuable DMA channel during half-duplex transfers. The register can only be read. Do not write to this register.
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Chapter 9 Synchronous Serial I/O (TXSEI)
9.3
TXSEI Operations
There are five signals associated with SEI transfers multiplexed on the PIO pins. The use of each signal depends on the mode (master/slave) of the SEI device. Because the SEI signals are on a shared pin it is necessary to deactivate PIOs 16, 17, 18, 19 and 22 by writing a zero to bits 16, 17, 18, 19 and 22 in the PMUX register. Furthermore the selection whether TXSEI or UART0 functionality is mapped to the corresponding pins has to be done via the Chip Configuration Register (CCR). A typical configuration consists out of one master device, which controls several slave devices. Only the master and one slave device are active at once. The master selects one slave for communication using the PORT pins to select each slave separately. Only the selected slave enables its port driver for the RX signal. TXSEI offers a dedicated Slave Select input, which allows it to act on busses with multiple master devices. The dedicated Slave Select input guarantees a fast response to master's device selection on the bus. PIO16/CLK(SEI)/CLK(SIO0) pin: In master mode the CLK pin is used as an output, in slave mode it functions as input. When TXSEI is configured as master, the CLK signal is derived from the internal TXSEI clock generator depending on the SEI polarity and clock rate settings. When the master initiates a transfer, a programmable number of 5 to 16 clock cycles are automatically generated on the CLK pin. When TXSEI is configured as a slave, the CLK pin synchronizes data output and input to and from the external master. In both the master and slave SEI device, data is shifted on one edge of the CLK signal and is sampled on the opposite edge where data is stable. The edge polarity is determined by the SEI transfer protocol.
PIO18/TX(SEI)/TX(SIO0) and PIO17/RX(SEI)/RX(SIO1) The RX and TX data pins are used for receiving and transmitting serial data. When the SEI is configured as a master, RX is the data input line, and TX is the master data output line. When the SEI is configured as a slave, these pins reverse roles.
PIO19/SSI(SEI)/CLK(SIO1) pin The Slave Select Input port is used in Slave mode. The Slave Select Input signal is active low. If TXSEI's Slave Select Input is inactive, TXSEI will not follow the transmissions on the SEI bus. If the Slave Select signal goes inactive during a running transfer and there are still other bits of the current transfer expected to receive, a Transfer Format Error will be signaled. The current value of the shift buffer will be transferred to the receive buffer despite of this error. When TXSEI is configured to be the master and the SSI pin is asserted a transmission error will be recognized. This function can be disabled with the SSIVAL bit in the SECR0 register.
PIO22/SSO(SEI)/RTS(SIO1) pin PIO22 is the dedicated slave select output signal and is asserted during transfer in master mode by the TXSEI device. In the case that the protocol of the connected device expects that the SS signal idles low for longer than 16 bits this signal must be generated using the PORT module.
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Preliminary
Chapter 9 Synchronous Serial I/O (TXSEI) 9.3.1 TXSEI Transfer Format
During an SEI transfer, data is simultaneously transmitted (shifted out serially) and received serially (shifted in serially). The serial clock synchronizes shifting and sampling of the information on the two serial data lines. The transfer format depends on the settings of the SPHA and SPOL registers in the SECR0 register. SPHA switches between two fundamentally different transfer protocols, which are described below. 9.3.1.1 SPHA Equals 0 Format
n= 5,6,...,16 Cycle # SCK (SPOL = 0) SCK (SPOL = 1) TX RX SS SRRDY 1 2 3 4 n-3 n-2 n-1 n
Sample Point
Figure 9.3.1 Protocol Timing for SPHA=0 In this transfer format, the bit value is captured on the first clock edge. This will be on a rising edge when SPOL equals zero and on a falling edge when SPOL equals one. The levels on the TX and RX signals change with the second clock edge on SCK. This clock edge will be a falling edge when SPOL equals zero and a rising edge, when SPOL equals one. With SPOL equal to zero, the shift clock will idle low. With SPOL equals 1 it will idle high. In master mode, when a transfer is initiated by writing a new value to the SEDR register the new data is placed on the TX signal for half a clock cycle before the shift clock starts to operate. After the last shift cycle, the STRDY and SRRDY flags will be asserted. In this format the SS signal has to be deasserted and reasserted between each successive frame. If the TXSEI is configured as a slave, SS has to be deasserted at least for the period of one TXSEI bit time (at least 8 system clocks).
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Chapter 9 Synchronous Serial I/O (TXSEI)
9.3.1.2 SPHA Equals 1 Format
n=5,6,...,16 Cycle # CLK (SPOL = 0) CLK (SPOL = 1) TX RX SS SRRDY 1 2 3 4 n-3 n-2 n-1 n
Sample Point
Figure 9.3.2 Protocol Timing for SPHA=1 In this transfer format, the first bit is shifted in on the second clock edge. This will be on a falling edge when SPOL equals 0 and on a rising edge when SPOL equals 1. If SPOL equals 0, the shift clock will idle low; with SPOL equals 1 it will idle high. In master mode, when a transfer is initiated by writing a new value to the SEDR register the new data is placed on the TX signal with the first edge of the shift clock. 9.3.1.3 Inter-Frame Space Delay Mechanism Due to its DMA support and its buffered shift register, TXSEI is able to sustain high data rates, with only a minimum amount of space between two consecutive frames. However, between consecutive transfers it still has to be ensured that the slave device can keep up with the transfer rate of the SEI master. If TXSEI is configured as a master, the slave device typically has to write new values to its transmit buffer, before the next transfer can be started. To allow this, usually a minimum inter-frame space is specified considering interrupt response and data fetch time of the slave device. TXSEI eases the implementation of this inter-frame space by offering an automated mechanism to guarantee inter-frame delays between consecutive frames. The inter-frame space counter is implemented as a 10 bit down counter. The counter is reloaded with the value from the SEFS register after each transfer. The next transfer will not start before the IFS counter reaches a value of zero. The internal IFS counter is reset every time the SEFS register is written. Therefore, if the module is in the inter-frame space the next transfer will start immediately, if the register is written, even if the same value is rewritten to the register.
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Chapter 9 Synchronous Serial I/O (TXSEI)
The following figure shows the function of the inter-frame space timer:
SCK Transfer IFSCounter StoreRxVal LoadTxVal
Transfer 1 Wait IFS Transfer 2
SEIFS
SEIFS-1
2
1
0
Figure 9.3.3 Waveform While Using Inter-Frame Space Timer
9.3.2
TXSEI Buffer Structure
TXSEI has both a transmit and a receive buffer. The buffers are implemented as FIFO and are able to store four frames each (one frame has a 16-bit length). When a new TXSEI transfer is started by writing the data register, the transfer value is first stored in TXSEI's transmit buffer. From there the value will be fetched by the shift register immediately, if the module is idle or after the currently running transfer has completed. A receive value from the shift register is stored in the receive buffer every time a transfer completes. TXSEI is able to generate interrupts depending on the fill-level of these buffers. Therefore, it is possible to refill the buffers with several values within one interrupt service routine, if desired.
9.3.2.1
TXSEI System Errors TXSEI is able to detect the following system errors during transfer:
9.3.2.2
SEOE - Overflow Error An Overflow Error will be generated, when the receive buffer is completely filled, while a new value has been completely received on the SEI bus. In this case the data of the last transfer in the receive buffer is overwritten with the new value and the SEOE flag in the SESR register is asserted. The SEOE register gives the programmer an indication, that data consistency during the transfer was lost.
9.3.2.3
SEUE - Underflow Error An Underflow Error is generated, if the module is in slave mode and the bus master performs a shift, when no output value has been specified by writing to the data register.
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Chapter 9 Synchronous Serial I/O (TXSEI)
9.3.2.4 SETF - Transfer Format Error This error is generated, if the transfer format is violated. There are two different scenarios, in which a Transfer Format Error could occur. In slave mode, a transfer format error will be signaled, if: * * * the slave select pin is used for TXSEI purpose (Configured in the port register) and TXSEI is in the middle of a transfer and the number of bits received yet is smaller than the number specified in the SSZ (SECR1) register
and if the slave select signal is set inactive at this point. It signals the user, that the master ended the transfer before the expected end of the transfer. A possible cause for this error could be different transfer length settings for master and slave devices. The partially received value will not be stored in the receive buffer since it is not complete. In master mode, a transfer format error will be signaled, if: * * * the slave select input signal is enabled in master mode (SSIVAL bit in SECR0 register) and both the master bit is set to one (MSTR bit in SECR0) and the system is in active mode (OPMODE="10" in SEMCR) and the Slave Select signal is asserted.
9.4
Interrupts
TXSEI connects to three interrupt signals. * * * SEIEXC: System Error Flags SEOE, SEUE, SETF, SIDLE (separately maskable) SEIRX Rx Buffer Fill Level Interrupt, Flag RBSI (not maskable) SEITX Tx Buffer Fill Level Interrupt, Flag TBSI (not maskable)
Interrupt SEIEXC is used for error detection purpose (SEOE, SEUE, SETF) and idle state interrupt (SIDLE). The interrupts SEIRX and SEITX are used to fetch and setup new data in an interrupt service routine for transferring data. All the interrupts will occur one system clock cycle later than the internal flags, which are visible in the status register.
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Chapter 9 Synchronous Serial I/O (TXSEI)
9-20
Preliminary
Chapter 10 Asynchronous Serial Interface (UART)
10. Asynchronous Serial Interface (UART)
The Asynchronous Serial Interface (UART) has the following features: * * * * * * Four channels Full-duplex transfer Baud rate generator Modem flow control (RTS/CTS), available on channels 1 and 2 only Transmit and receive FIFO, each of size 2 entries Multi controller system support (master/slave* operation capable)
10.1 Operations on Serial Interface
10.1.1 Outline
The UART is used to convert parallel data, retrieved from memory, to a serial stream with control and error detection bits. The same applies for data receive: only that a serial stream of data is converted to parallel by means of a shift register and then put into a FIFO. To retrieve data from memory or store data into memory one of the following policies is available: * * * polling the Interrupt Status Register by serving an interrupt by DMA transfer.
The rate at which data is transferred (Baud Rate) can be programmed in the Baud Rate Control Register. Care has to be taken in the configuration of the TMPR3916 to enable the I/Os of the UART.
*
Please read carefully the documentation if the device has to be used for slave operation, since the TMPR3916 does not have open drain output pins.
10-1
Preliminary
Chapter 10 Asynchronous Serial Interface (UART)
DataFromSystemBus(7:0)
STATUS REGISTER SystemBusData(31:0)
BAUD RATE GENERATOR
TX FIFO and PARALLEL IN / SERIAL OUT (PISO)
SerialDataOut CTS_n
TX FIFO Status SystemBusControl SerialClockOut Control Bus
RX FIFO Status & RX Error Flags SERIAL IN / PARALLEL OUT (SIPO) and RX FIFO
SerialDataIn RTS_n
DataToSystemBus(7:0) RXDmaReq_n TXDmaReq_n RXDmaAck_n TXDmaAck_n
Figure 10.1.1 UART Block Diagram
10.1.2
Data Format
There are several data formats, which can be applied for serial I/O, these are summarized here: Data length Stop bit Parity bit Parity system Start bit data format 7 - 8 - 9 bits (9-bit data is practicable for a multi controller system) 1 - 2 bits provided/not provided even/odd 1-bit fixed MSB/LSB first (switchable by register settings)
Please note that sending a parity bit is not allowed for address transmission in a multi-controller system, Figure 10.1.2 and Figure 10.1.3 show examples for these data formats:
ExternalClock
SystemClock
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Preliminary
Chapter 10 Asynchronous Serial Interface (UART)
8-bit data 1 2 3 4 5 6 7 8 9 10 11 12
St art
bi 0 t
bi 1 t
bi 2 t
bi 3 t
bi 4 t
bi 5 t
bi 6 t
bi 7 t
Pari y t
st op
st op
St art
bi 0 t
bi 1 t
bi 2 t
bi 3 t
bi 4 t
bi 5 t
bi 6 t
bi 7 t
Pari y t
st op
St art
bi 0 t
bi 1 t
bi 2 t
bi 3 t
bi 4 t
bi 5 t
bi 6 t
bi 7 t
st op
st op
St art
bi 0 t
bi 1 t
bi 2 t
bi 3 t
bi 4 t
bi 5 t
bi 6 t
bi 7 t
st op
7-bit data 1
2
3
4
5
6
7
8
9
10
11
12
St art
bi 0 t
bi 1 t
bi 2 t
bi 3 t
bi 4 t
bi 5 t
bi 6 t
Pari y t
st op
st op
St art
bi 0 t
bi 1 t
bi 2 t
bi 3 t
bi 4 t
bi 5 t
bi 6 t
Pari y t
st op
St art
bi 0 t
bi 1 t
bi 2 t
bi 3 t
bi 4 t
bi 5 t
bi 6 t
st op
st op
St art
bi 0 t
bi 1 t
bi 2 t
bi 3 t
bi 4 t
bi 5 t
bi 6 t
st op
Figure 10.1.2 8 Bit and 7 Bit Data Format for Single Controller Mode, Data Formats are Shown for 1 and 2 Stop Bits, with and without Parity
8-bit data multi control system
W U B =W ake U p B i t 1: A ddress ( )f ID ram e 0: D at f a ram e
1
2
3
4
5
6
7
8
9
10
11
12
St art
bi 0 t
bi 1 t
bi 2 t
bi 3 t
bi 4 t
bi 5 t
bi 6 t
bi 7 t
v ta
st op
st op
St art
bi 0 t
bi 1 t
bi 2 t
bi 3 t
bi 4 t
bi 5 t
bi 6 t
bi 7 t
v ta
st op
7-bit data multi control system 1 2 3 4 5 6 7 8 9 10 11 12
St art
bi 0 t
bi 1 t
bi 2 t
bi 3 t
bi 4 t
bi 5 t
bi 6 t
v ta
st op
st op
St art
bi 0 t
bi 1 t
bi 2 t
bi 3 t
bi 4 t
bi 5 t
bi 6 t
v ta
st op
Figure 10.1.3 Multi Controller Mode Transmission, 7 and 8 Bit Data Formats are Shown with 1 or 2 Stop Bits, Parity Check is not Available in Multi Controller Mode
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Preliminary
Chapter 10 Asynchronous Serial Interface (UART) 10.1.3 Serial Clock Generator
The data rate of serial transmissions depends on the Serial Clock. To generate the Serial Clock it is possible to use either an external clock or the system clock of the device. Please note that once an external clock is connected to the device's I/O pin the user must use this clock, otherwise a conflict will occur. Once that the clock source is fixed, this is used to generate the Serial Clock by means of a prescaler (optional) and a Baud Rate Divisor. Figure 10.1.4 shows a block diagram of the Serial Clock Generator:
OUTSEL
T0 external clock 1/16 T2 T4 SIOCLK T6 system clock Selector Prescaler Prescale Select Clock Select 1 Selector Divider
Selector
Baud Rate Generator
Baud Rate Divider Value
Clock Select 2
Figure 10.1.4 Serial Clock Generator Structure The Clock Select 1 and 2 control lines are bits 6 and 5 respectively of the Line Control Register and allow the user to choose between an internal or external clock, and if the Baud Rate Generator has to be bypassed. The output clock - if the BRG is bypassed - can be of the same frequency as the input clock or divided by 16, depending on the value of OUTSEL (Line Control Register). The SIOCLK is not used as system clock for FIFOs etc, but to synchronize operations. The SIOCLK is output as Serial Clock Out. The OUTSEL bit will affect the frequency of the Serial Clock Out but not the baud rate of the UART. The baud rate generator creates the transmit/receive clock, which regulates the transfer rate for the serial interface. The baud rate can be calculated by the following formula:
baud rate =
input frequency x prescaler / 16 (divisor of baud rate generator + 1)
The input clock (either system or external clock) may be prescaled by the values shown in the SIBGR registers and then divided according to the BRD field of the same register. Pay attention to the fact that the clock is actually divided by a value of (BRD+1). The BRD is an 8-bit register, so the divider ranges from 1 to 256. Table 10.1.1 shows the output frequency of the baud rate generator (SIOCLK), depending on the baud rate divisor and the prescaler:
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Preliminary
Chapter 10 Asynchronous Serial Interface (UART)
Desired Baud Rate
9600 57600 115200
Baud Rate Input
60 MHz 60 MHz 60 MHz
Prescaler
1/2 (000) 1/2 (000) 1/2 (000)
Baud Rate Divisor
194 (0xC2) 32 (0x20) 15 (0x0F)
Actual Baud Rate
9615 56818 117187
Table 10.1.1 Baud Rate Register Settings for Common Baud Rates Other Baud Rates may be easily calculated. When choosing the value of the Prescaler and the Baud Rate Divisor we recommend that the actual baud rate should not differ more than 4.0% from the nominal value. This is because a certain drift is allowed but if the 4.0% figure is exceeded then the correct transmission of a frame is not guaranteed anymore.
10.1.4
Transmitter Control
Once that the parameters have been set, writing data into the Transmit FIFO is sufficient for transmission. During transmission also the parity bit will be calculated and added to the data stream if the option has been enabled. The data transmission rate will be the one set in the Baud Rate Register. Make sure that both receiver and transmitter have the same settings for Baud Rate, data bits, parity, and stop bits. The transmitter shift register is an 8-bit shift register, that gets its data from the transmitter FIFO. Bit 0 of the shift register will be sent first.
10.1.5
Receiver Control
After that the receiver is enabled, the controller will be looking for the start bit on the serial input line (RX). A "0" on serial input only will be recognized as start bit, if a "1" was detected in the bit before. When the receive control detects a start bit, the receiving operation will start. The output of the baud rate generator (SIOCLK) is 16 times the frequency of the data transfer rate on serial interface. The serial data input (RX) will be sampled on 7th, 8th and 9th clock of SIOCLK. A majority logic determines the input value. The receiver shift register consists of an 8-bit shift register. At the end of a transmission, bit 0 of the shift register contains the bit which has been received first.
10.1.6
Host Interface
The data transfer to the transmitter FIFO can be handled via interrupt processing or via DMA transfer. If the transmitter FIFO has as many free entries as set in the transmit DMA interrupt trigger level (TDIL in FIFO control register), an interrupt or DMA request is generated. Afterwards the DMA Controller or the software fetches data from memory and writes it to the transmitter FIFO. The data transfer from the receiver FIFO can be handled via polling, interrupt processing or via DMA transfer. If the receiver FIFO has as much free space as set in the receive DMA interrupt trigger level (RDIL in FIFO control register), an interrupt or DMA request is generated. Afterwards the DMA Controller or the software fetches data from the receive FIFO and writes it to memory.
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Chapter 10 Asynchronous Serial Interface (UART)
The following settings of TDR, RDR, TIR and RIR of Interrupt Control Register (SIDICR) are allowed: TDR
0 0 0 0 0 0 1 1 1
RDR
0 0 0 0 1 1 0 0 1
TIR
0 0 1 1 0 1 0 0 0
RIR
0 1 0 1 0 0 0 1 0
Transmit
TDIS polling TDIS polling Interrupt Interrupt TDIS polling Interrupt DMA DMA DMA
Receive
RDIS polling Interrupt RDIS polling Interrupt DMA DMA RDIS polling Interrupt DMA
Table 10.1.2 DMA/Interrupt Control Register Settings for Host Interface Operation
10.1.7
Flow Control
Transmission enable can be set either * * via software control by a transmit serial data request of the MPU (TSDR). via hardware control.
When the transmit enable becomes inactive, the transmission will be suspended after the completion of the current frame transmission. Reception is enabled either * * via RTS software control of the MPU (RTSSC) or via hardware control.
For hardware control, the flow control offers the possibility of a DMA transfer or an interrupt request. This choice can be made by configuring the Interrupt Control Register (SIDICR). Remember that RTS/CTS flow control has to be enabled by Flow Control Register (SIFLCR). During transfers, the receiver can ask for a temporary suspension by setting to 1 the RTS signal. The transmission is resumed by setting to 0 the RTS signal when the receiver is ready to accept new data. Frame by frame data transfer is available by setting the transmitter to hardware control (TES=1) and the receiver RTSTR to 1 (handshaking).
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Chapter 10 Asynchronous Serial Interface (UART) 10.1.8 Parity Control
During transmission, parity information is generated when the data is written to the transmitter shift register. The information is stored * * in bit 7 of the transmitter shift register for 7-bit data length or in TWUB of the line control register for 8-bit data length.
During reception, the parity check is executed when the data is written from receiver shift register to the receiver buffer. A parity error occurs when a difference between received and calculated parity bit is found. The check information is stored * * in bit 7 of the read buffer for 7-bit data length or in RWUB of the line control register for 8-bit data length.
10.1.9
Interrupts
The UART can send three interrupt signals to the Interrupt Controller of the TMPR3916: * * * Transmit Interrupt Receive Interrupt Exception Interrupt
A brief explanation of the meaning of each of these interrupts now follows, for further details refer to the Registers section of the document. It is possible to mask the interrupts by programming the SIDICR register. The cause of the interrupt, however, is latched and available for polling. Transmit Interrupt A Transmit Interrupt may occur when: * There is free space in the TX FIFO, hence new data may be written in the FIFO.
Receive Interrupt A Receive Interrupt may occur when: * * * There is valid data in the RX FIFO, which has not been retrieved yet. There is a Time Out on the Receiver and the Time Out is mapped on the RX interrupt (programming RIR bit of Interrupt Control Register) There is an error (parity, frame or overrun) detected in the RX FIFO.
Exception Interrupt A Status Interrupt may occur when: * * * * * * * There is a BREAK in the UART transfer (see section "10.1.11 Breaks"). All data in transmit FIFO has been sent. There is free space in TX FIFO. A CTS active has been detected by the transmitter. There is an Overrun Error. There is a Frame error. There is a Parity error.
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Chapter 10 Asynchronous Serial Interface (UART) 10.1.10 Error Flags
The following error flags can be risen: Overrun error Occurs when there is an overflow of the transmit or of the receive buffer. Parity error Occurs when the received parity bit and the calculated parity information are not the same. Frame error Occurs when 0 is detected at the stop bit position during receive.
10.1.11 Breaks
A break is detected by the receiver when all bits in a frame are 0 and the stop bit is also 0. When a break is detected the received data will not be stored and the UART will assert an interrupt to signal the break condition. To transmit a break, the TBRK bit of the flow control register must be set to 1. To resume normal operation the TBRK bit must be set to 0 again.
10.1.12 Receiver Time Out
A receiver time out occurs when the receiver FIFO has at least 1 entry stored and an equivalent of a 2-byte receive time is elapsed from the previous reception. That sets the receiver Time Out bit (TOUT) in the DMA/Interrupt Status register(SIDISR). Please note that if all data has been fetched from the FIFO, the Time Out will not be set! It is recommended not to use the TOUT bit for flow control of the receiver.
10.1.13 Handling of received data and receiver FIFO status bits
The following status information is stored in the receiver FIFO along with the received data: * * * * * UART receiver break (UBRK) UART available status (UVALID) UART frame error (UFER) UART parity error (UPER) UART overrun error (UOER)
The software can read the status in the DMA/interrupt status register (SIDISR). The status of this register is updated always after data has been read from the FIFO: if there are 2 entries in the FIFO, and the second one contains a parity error, this will be signaled in the SIDISR only after the first entry has been read. Data that has been received without errors can be read from the receiver FIFO. A Receive Interrupt Request will indicate the presence of new entries in receiver FIFO, if this is enabled. Errors during reception will be indicated by an exception interrupt request. Only data that has been received without errors is transferable via DMA. When an error (UFER, UPER, UOER) or a receive time-out (TOUT) occurs, the receive error is notified and the received data transfer request is not asserted.
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Chapter 10 Asynchronous Serial Interface (UART) 10.1.14 Multi Controller Systems
When UMODE in the Line Control Register (SILCR) is 0x2 or 0x3, the UART changes into the multi controller system mode. In a multi controller system, the master controller sends data to the selected slave controllers. The slaves will be selected by sending an address ID before sending the data. Nonselected slave controllers will ignore the data. Setting the WUB of the transmit frame to 1 indicates the transmission of an address ID. Data frames, instead, will have the WUB set to 0. It is up to the software to compare the addresses and eventually enable the reception of Data Frames. Protocol of multi controller system: (1) Master and slave controllers must have the UMODE field 10 or 11 in the Line Control Register to operate in multi controller mode. (2) Software sets the RWUB in the Line Control Register to 1 - for each slave controller - to be ready to receive the address ID frame from the master controller. (3) Software sets the WUB of the transmit frame to 1 (Line Control Register WUB=1) - in the master controller - to send the slave controller address ID (7- or 8-bit length). (4) An interrupt is generated in a slave controller when RWUB in Line Control Register is 1 and WUB of the received data frame is 1 (receive data is an address frame). The software compares its address ID with the received address ID and sets RWUB to 0 when both match. The last operation enables the selected slave to receive data frames. (5) Then software must set the WUB of the Line Control Register to 0 to enable the transmission of data frames for the master controller. If this operation is not performed the WUB in the transmitted frames will be 1, and the slaves will understand the incoming frames as address frames. When the selected slave controller (i.e. the controller whose address matched with the one sent by the master) receives data, an interrupt is generated. A non selected slave controller will have the RWUB still set to 1, incoming data frames will be ignored. The slave controllers can send data only to the master controller. An example of the multi controller system configuration is shown in Figure 10.1.5
Master SOUT SIN TX RX
RX TX SIN SOUT Slave#1
RX TX SIN SOUT Slave#2
RX TX SIN SOUT Slave#3
Figure 10.1.5 Example Configuration for Multi Controller System IMPORTANT: The TMPR3916 does not have Open Drain capability on its output pins. A configuration as the one depicted in Figure 10.1.5 is possible only if external logic is added on the board.
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Chapter 10 Asynchronous Serial Interface (UART)
10.2 Registers
10.2.1 Overview
Physical Address (hex)
1C00 0000 1C00 0004 1C00 0008 1C00 000C 1C00 0010 1C00 0014 1C00 0018 1C00 001C 1C00 0020
Register (short name)
SILCR SIDICR SIDISR SISCISR SIFCR SIFLCR SIBGR SITFIFO SIRFIFO
Name
Line Control Register DMA/Interrupt Control Register DMA/Interrupt Status Register Status Change Register FIFO Control Register Flow Control Register Baud Rate Control Register Transmitter FIFO Register Receiver FIFO Register
Function
Specify data format Controls settings about interrupt and DMA requests Shows status information about interrupt and DMA requests Shows status information of UART transfer Controls settings of transmit/ receive FIFO Controls running transmission Contains baud rate settings Transmit data Received data
This table includes the addresses of UART channel 0. Channel 1 uses the addresses 1C00 0040 to 1C00 0060. Channel 2 uses the addresses 1C00 0080 to 1C00 00A0. Channel 3 uses the addresses 1C00 00C0 to 1C00 00E0.
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Chapter 10 Asynchronous Serial Interface (UART) 10.2.2
Bit Name Bit Name Bit Name 15 RWUB 7 14 TWUB 6 SCS 13 5 4 UEPS 12 3 UPEN
Line Control Register (SILCR)
31 11 10 OUTSEL 2 USBL 9 IRDA 1 UMODE 8 LSBF 0 16
Bit
31:16 15
Name
RWUB Wired to zero
Function
Reset Value
0 0
R/W
R R/W
Wake Up Bit for Receive 0 = The UART does not wait for a wake-up-bit 1 = The UART is looking for a wake-up-bit Used only in multi controller mode. Wake Up Bit for Transmit 0 = Next frame contains data (wake-up-bit = 0) 1 = Next frame contains address (wake-up-bit = 1) The contents of this bit make only sense in multi controller mode. Not used / Always write to "0" Wired to zero Clock Output Select 0 = Clock frequency is the same as in Baud Rate Register (SIBGR) specified 1 = Clock frequency is 16 times the value specified in Baud Rate Register (SIBGR) IrDA Clock 0 = No output of IrDA clock 1 = Output of IrDA clock It has no meaning when OUTSEL = 1. LSB First 0 = Reads or sends the MSB first 1 = Reads or sends the LSB first Wired to zero SIO Clock Select 00 = Internal system clock 01 = Baud rate generator provided with internal clock 10 = External clock 11 = Baud rate generator provided with external clock UART Parity Select 0 = Odd Parity 1 = Even Parity UART Parity Enable 0 = Disable Parity Check 1 = Enable Parity Check The bit should be 0 in the multi controller system mode (UMODE = 10, 11). UART Stop Bit Length 0 = 1 bit 1 = 2 bit
14
TWUB
1
R/W
13 12:11 10
OUTSEL
0 00 0
R/W R R/W
9
IRDA
0
R/W
8
LSBF
0
R/W
7 6:5
SCS
0 10
R R/W
4
UEPS
0
R/W
3
UPEN
0
R/W
2
USBL
0
R/W
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Chapter 10 Asynchronous Serial Interface (UART)
Bit
1:0
Name
UMODE
Function
UART Mode For the SIO Mode setting. 00 = 8-bit data length 01 = 7-bit data length 10 = Multi controller 8-bit data length 11 = Multi controller 7-bit data length
Reset Value
00
R/W
R/W
The reception of a 1-bit stop while in a 2-bit stop length setting does not generate a frame error. When an external clock is connected to the Serial Clock In pin of the TMPR3916, bit 6 of the SILCR must be set to 1 to avoid conflicts. It is not possible to connect an external clock and decide to use the system clock for UART operation. The OUTSEL bit will have effect only on the frequency of the Serial Clock Out. The Baud rate of the UART will not depend on the settings of the OUTSEL bit. The Wake Up Bit for Receive has to be set to 1 if the receiver has to be enabled for receiving an address frame prior to the data frames. The Wake Up Bit for Transmit has to be set to 1 if an address frame is being sent prior to sending data frames (an address frame may be followed by several data frames to the same receiver). Obviously these two bits make sense only in multi controller mode. In a point-to-point transmission there's no need to address the receiver.
10.2.3
Bit
DMA/Interrupt Control Register (SIDICR)
31 15 TDR 7 14 RDR 6 13 TIR 5 SIOE 12 RIR 4 SICTS 11 SPIR 3 SIBRK 2 SITR 10 CTSAC 1 SIAS 9 8 0 SIUB 16
Name Bit Name Bit Name
Bit
31:16 15
Name
TDR Wired to zero
Function
Reset Value
0 0
R/W
R R/W
Transmit DMA Request 0 = No DMA request when free space in transmit FIFO 1 = DMA request when free space in transmit FIFO Receive DMA Request 0 = No DMA request when data in receive FIFO 1 = DMA request when data in receive FIFO Transmit Interrupt Request 0 = No interrupt when free space in transmit FIFO 1 = Send SIOTX interrupt when free space in transmit FIFO Receive Interrupt Request 0 = No interrupt when error or time out occurs 1 = When error or time-out occurs send * SIORX interrupt, when RDR=0, * SIOEXC interrupt, when RDR=1
14
RDR
0
R/W
13
TIR
0
R/W
12
RIR
0
R/W
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Chapter 10 Asynchronous Serial Interface (UART)
Bit
11
Name
SPIR
Function
Special Interrupt Request 0 = No interrupt when errors occur 1 = Send SIOEXC interrupt, when errors occur CTSS Status Active Condition Sets condition of CTS. 00 = Disable CTS 01 = CTS terminal rising edge 10 = CTS terminal falling edge 11 = Both edges Wired to zero Special Interrupt on Overrun Error 0 = No actions on overrun error 1 = When an overrun error occurs, send SIOEXC interrupt and set STIS bit in Interrupt Status Register (SIDISR) Special Interrupt on Receive of CTS 0 = No actions on CTS 1 = When receiving CTS, send SIOEXC interrupt and set STIS bit in Interrupt Status Register (SIDISR) Special Interrupt on Break of UART Transfer 0 = No actions on break 1 = When a break occurs, send SIOEXC interrupt and set STIS bit in Interrupt Status Register (SIDISR) This bit must have the same value of SIUB Special Interrupt on Free Space in Transmit FIFO (RBRKD) 0 = No actions on free space in transmit FIFO 1 = When free space is detected, send SIOEXC interrupt and set STIS bit in Interrupt Status Register (SIDISR) Special Interrupt, when all data sent 0 = No actions, when all data sent 1 = When all data sent, transmit SIOEXC interrupt and set STIS bit in Interrupt Status Register (SIDISR) Special Interrupt on Break of UART Transfer (UBRKD) 0 = No actions on break 1 = When a break occurs, send SIOEXC interrupt and set STIS bit in Interrupt Status Register (SIDISR) This bit must have the same value of SIBRK
Reset Value
0
R/W
R/W
10:9
CTSAC
0
R/W
8:6 5
SIOE
0 0
R R/W
4
SICTS
0
R/W
3
SIBRK
0
R/W
2
SITR
0
R/W
1
SIAS
0
R/W
0
SIUB
0
R/W
The SIUB and SIBRK bits have the same behavior for the Exception Interrupt, since there is only one Break flag in the DMA/Interrupt Status Register (SIDISR). However the SIBRK masks the UART being in break status, the SIUB masks the detection of a BREAK. Obviously as soon as a Break is detected (if any of the two is unmasked) the UART will send an Interrupt Request. To know if a Break has already occurred or is still active refer to the Status Change Register (SISCIR). Setting these two bits to 1 or 0 will not affect the behavior of the Status Change Register.
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Chapter 10 Asynchronous Serial Interface (UART) 10.2.4
Bit Name Bit Name Bit Name 15 UBRK 7 RDIS 14 UVALID 6 STIS 13 UFER 5 12 UPER 4
DMA/Interrupt Status Register
31 11 UOER 3 10 ERI 2 RFDN 9 TOUT 1 8 TDIS 0 16
Bit
31:16 15 14
Name
UBRK UVALID Wired to zero
Function
Reset Value
0 0 1
R/W
R R R
Break This bit will be set to 1, when break is detected No Data Available This bit will be set to 1, when the receiver FIFO contains no data. Frame Error This bit will be set to 1, when an error occurred during transfer of the current frame. Parity Error This bit will be set to 1, when a parity error has been detected. Over Run Error This bit will be set to 1, when an overrun error has occurred. Error Interrupt This bit will be set to 1, when a frame error, parity error or overrun error has occurred. Writing 0 to this bit clears it. Writing 1 does not change contents of this bit. Receive Time Out This bit will be set to 1 immediately after a receive time out occurs. Writing 0 to this bit clears it. Writing 1 does not change contents of this bit. Transmit DMA/Interrupt Status This bit will be set to 1, when there is free space in the transmit FIFO. Receive DMA/Interrupt Status This bit will be set to 1, when there are valid data in the receive FIFO. Status Interrupt Status This bit will be set to 1, when the status, selected in STIR of Interrupt Control Register (SIDICE), has changed. Wired to zero Receive FIFO Data Number Status Indicating the number of received data frames stored in the receiver FIFO (0 to 2 entries).
13
UFER
0
R
12 11 10
UPER UOER ERI
0 0 0
R R R/W
9
TOUT
0
R/W
8 7 6
TDIS RDIS STIS
1 0 0
R/W R/W R/W
5 4:0
RFDN
0 00000
R R/W
UBRK, UPER and UOER show the status of the upper FIFO entry. After reading the next data entry, the UART will update the status information in UBRK, UPER and UOER. That is the reason, why the software must read status information before reading the data.
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Chapter 10 Asynchronous Serial Interface (UART) 10.2.5
Bit Name Bit Name 7 6 5 OERS 4 CTSS
Status Change Register (SISCISR)
31 3 RBRKD 2 TRDY 1 TXALS 0 UBRKD 8
Bit
31:6 5
Name
OERS Wired to zero
Function
Reset Value
0 0
R/W
R R/W
Overrun Error This bit will be set to 1, when an overrun error occurs. Cleared by writing 0 CTS terminal Indicates the CTS terminal status. 0 = CTS is deasserted 1 = CTS is asserted Receive Break This bit will be set to 1, when the UART is in break status. Tx Ready Set to 1 when the transmitter FIFO has free space at least for one entry of data. Tx All Set to 1 when transmitter FIFO and transmitter shift register are empty. UART Break Detect Set to 1 immediately when a break is detected. Cleared by writing 0.
4
CTSS
0
R
3
RBRKD
0
R
2
TRDY
1
R
1
TXALS
1
R
0
UBRKD
0
R/W
UBRKD will be set to 1 as soon as a Break is detected, it will remain 1 until it is explicitly cleared by the software. RBRKD, instead, will be 1 only for the duration of the Break.
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Chapter 10 Asynchronous Serial Interface (UART) 10.2.6
Bit Name Bit Name Bit Name 15 SWRST 7 RDIL 6 5 4 TDIL 14 13 12 3 2 TFRST 1 RFRST
FIFO control register (SIFCR)
31 11 10 9 8 RDIL 0 FRSTEW 16
Bit
31:16 15
Name
SWRST Wired to zero
Function
Reset Value
0 0
R/W
R W
Software Reset 0 = Normal operation 1 = Softreset of UART This software reset lasts for 4 clock cycles. The channel will not react to any requests during this time period. Warning: While using instruction cache of TX39 the following problem occurs: As it takes about 5 clock cycles to activate software reset this might affect the next write action to a register of the channel being reset. Solution: Insert other instructions between resetting command and next write command of the same channel. Wired to zero Receive DMA/Interrupt trigger level These bits determine at which fill level of the receive FIFO the UART sends an interrupt or DMA request. 00 = If 1 byte in receive FIFO make a request 01 = If 2 bytes in receive FIFO make a request others = invalid setting Wired to zero Transmit DMA/Interrupt trigger level These bits determine at which fill level of the transmit FIFO the UART sends an interrupt or DMA request. 00 = If 1 byte in transmit FIFO make a request 01 = If 2 bytes in transmit FIFO make a request others = Invalid setting Transmit FIFO Reset 0 = Normal operation 1 = Reset of transmit FIFO (only when FRSTEW = 1) Receive FIFO Reset 0 = Normal operation 1 = Reset of receive FIFO (only when FRDTEW = 1) FIFO Reset Enable 0 = Resets of receive and transmit FIFO are inhibited 1 = Resets of receive and transmit FIFO are possible
14:9 8:7
RDIL
0 00
R R/W
6:5 4:3
TDIL
0 00
R R/W
2
TFRST
0
R/W
1
RFRST
0
R/W
0
FRSTEW
0
R/W
To properly reset the Receiver or the Transmitter FIFO, bit FRSTEW has to be set to 1 together and at the same time in which TFRST or RFRST are set to 1. E.g.: to reset the Receiver FIFO value 0x00000003 must be written. This operation will reset the Receiver FIFO until either RFRST or FRSTEW are set to 0 again by writing in the SIFCR register To perform a software reset, the value of the FRSTEW bit is meaningless.
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Chapter 10 Asynchronous Serial Interface (UART) 10.2.7
Bit Name Bit Name Bit Name 7 TSDR 15 14 6 5 13 12 RCS 4
Flow control register (SIFLCR)
31 11 TRS 3 RTSTL 10 2 9 RTSSC 1 8 RSDR 0 TBRK 16
Bit
31:13 12
Name
RCS Wired to zero
Function
Reset Value
0 0
R/W
R R/W
RTS Control Select Selects the method to control the RTS terminal. 0 = Software control 1 = Software or hardware control Tx Request Select Selects the transmit request. 0 = Control by transmit serial data request (TSDR). 1 = Control by transmit request command or the CTS terminal (hardware control) Wired to zero RTS Software Control Determines the output of the RTS terminal. 0 = Sets the RTS terminal to 0 1 = Sets the RTS terminal to 1 Receive Serial Data Request 0 = Received data will stored 1 = Received data will not be written into FIFO Transmit Serial Data Request 0 = Transmission runs 1 = Halts transmission. A running transmission will be finished. Wired to zero RTS Trigger Level Sets the RTS hardware control assert level at the number of receive data entries in the receiver FIFO. Possible settings: 01, 10 Transmitter Break 0 = Normal operation 1 = Transmit a break
11
TRS
0
R/W
10 9
RTSSC
0 0
R R/W
8
RSDR
1
R/W
7
TSDR
1
R/W
6:2 1
RTSTL
0 1
R R/W
0
TBRK
0
R/W
When the RSDR bit is set to 1, received data will be ignored: it will not be written into FIFO. Frame, Overrun and parity errors will not be generated.
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Chapter 10 Asynchronous Serial Interface (UART) 10.2.8
Bit Name Bit Name 15 11 10 9 BCLK
Baud rate control register (SIBGR)
31 8 7 BRD 0 16
Bit
31:11 10:8
Name
BCLK Wired to zero
Function
Reset Value
0 011
R/W
R R/W
Baud Rate Generator Clock Specifies the prescaler for the input clock of baud rate generator. 000 = 1/2 system frequency 001 = 1/8 system frequency 010 = 1/32 system frequency 011 = 1/128 system frequency 1xx = system frequency (prescaler bypass) Baud Rate Divisor Set the baud rate divisor.
7:0
BRD
0xFF
R/W
10.2.9
Bit
Transmitter FIFO register (SITFIFO)
31 8 7 TXD 0
Name
Bit
31:8 7:0
Name
TXD Wired to zero
Function
Reset Value
0 0
R/W
R W
Transmit data Data written to this register are carried to transmit FIFO. Note: The bits are write-only.
10.2.10 Receiver FIFO register (SIRFIFO)
Bit Name 31 8 7 RXD 0
Bit
31:8 7:0
Name
RXD Wired to zero
Function
Reset Value
0 0
R/W
R R
Receive Data Read this register to get next data item from the receiver FIFO.
The Receiver FIFO Register can only be read by a 32-bit-word access.
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Chapter 10 Asynchronous Serial Interface (UART)
10.3 Timings
Receive operation: (7, 8-bit data length)
1 SIOCLK SIN data SINTREQ* SINTREQ* SINTREQ* bit0 Valid bit0 bit7 Valid bit7 Parity bit Stop bit 7 8 9 10 11 16 7 8 9 10 11 16 1 7 8 9 10 11 16 1 7 8 9 10 11 16
DMA/Interrupt Status Reg. =1
Overrun Error If Parity Error Occur DMA/Interrupt Status Reg. =1 If Framing Error Occur
DMA/Interrupt Status Reg. =1
Figure 10.3.1 Receiving 7 or 8 Bit Data
Receive operation: (7, 8-bit length multi controller system; RWUB=1 for ID receive standby)
1 SIOCLK SIN data SPINTREQ* bit0 Valid bit0 bit7 Valid bit7 Wake Up bit =1 Stop bit 7 8 9 10 11 16 7 8 9 10 11 16 1 7 8 9 10 11 16 1 7 8 9 10 11 16
DMA/Interrupt Status Reg. =1
Overrun Error
SPINTREQ* SPINTREQ* If Framing Error Occur
DMA/Interrupt Status Reg. =1
Figure 10.3.2 Receiving 7 or 8 Bit ID in Multi Controller Environment
Receive operation: (7, 8-bit length multi controller system; RWUB=0 for data receive standby)
1 SIOCLK SIN data SPINTREQ* SPINTREQ* SPINTREQ* If Framing Error Occur bit0 Valid bit0 bit7 Valid bit7 Wake Up bit = 0 Stop bit 7 8 9 10 11 16 7 8 9 10 11 16 1 7 8 9 10 11 16 1 7 8 9 10 11 16
DMA/Interrupt Status Reg. =1
Overrun Error
DMA/Interrupt Status Reg. =1
Figure 10.3.3 Receiving 7 or 8 Bit Data in Multi Controller Environment
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Chapter 10 Asynchronous Serial Interface (UART)
Receive operation: (7, 8-bit length multi controller system; RWUB=1 for data skip)
1 SIOCLK SIN data SPINTREQ* SPINTREQ* SPINTREQ* If Framing Error Occur bit0 Valid bit0 bit7 Valid bit7 Wake Up bit = 0 Stop bit 7 8 9 10 11 16 7 8 9 10 11 16 1 7 8 9 10 11 16 1 7 8 9 10 11 16
DMA/Interrupt Status Reg. =1
Over Run Error
DMA/Interrupt Status Reg. =1
Figure 10.3.4 Receiving 7 or 8 Bit Data Skip Multi Controller Environment
Transmit operation
16 1 SIOCLK Shift-Out Timing SOUT TRANS. FIFO to Trans. Shift Reg. Start Bit bit0 bit n bit7 Parity Bit (Wake Up Bit) Stop Bit 16 1 16 1 16 1 16 1 16 1 16
Figure 10.3.5 Transmitting 8 Bit Data
Transmit halt timing by CTS*
16 1 SIOCLK CTS* Shift-Out Timing SOUT TRANS. FIFO to Trans. Shift Reg. Trans,start Stop Bit Start Bit bit0 bit n 16 1 16 1 16 1 16
Trans. halt
Figure 10.3.6 Transmitting HALT Command When CTS becomes 1 during data transmission, the data transfer halts after completing the current data transmission. Despite the halt, the next data is stored in the transmitter shift register. The transmission is restarted at the first shift out pulse after CTS becomes low.
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Chapter 10 Asynchronous Serial Interface (UART)
10.4 Flow Charts
In this paragraph some flow charts are presented, which should help the user to perform basic operations on the UART. In these examples an upper layer which involves a software protocol is used: the transmitter will send as first data frame a "block length" which will be used by the receiver to determine the number of incoming data frames. So if n data frames have to be transmitted, the actual length of the transmission will be of n+1 since the protocol uses the first frame as a control frame. The user may choose to implement or not such a protocol, the reason for using it here is to give an easy example on how to operate the UART. It is not recommended to use the Timeout error in the receiver to determine the end of a transmission: if the FIFO is empty the error will not occur. This bit is not suitable for flow control.
10.4.1
Transmitter programming
Figure 10.4.1 shows a basic example of transmission operation. The hardware RTS/CTS flow control is used, the other parameters refer to: * * * * * 8 bit data length 1 stop bit even parity MSB first software operates in polling mode on the TX FIFO
10-21
Preliminary
Chapter 10 Asynchronous Serial Interface (UART)
START
TMPR3916 CCR REGISTER & MUX CONFIGURATION
0
Reset UART: (SIFCR) SWRST = 1 TFRST = 1 FRSTEW = 1
1
Check TXALS in SISCISR (TX FIFO empty)
Line Control Register: LSBF = 0 UEPS = 1 UPEN = 1 (Sets MSB first, 8 bit tx, etc)
yes
BLOCK LENGTH > 0?
no
TRANSMISSION ENDS
Interrupt Control Register: CTSAC = 01 sets CTS active status to rising edge
Stop UART Reset (SIFCR) TFRST = 0 FRSTEW = 0
BLOCK LENGTH = BLOCK LENGTH - 2
BLOCK LENGTH = BLOCK LENGTH - 1
Flow Control Register TRS = 1 RSDR = 0 TSDR = 0 enables CTS hardware, storing of received data.
STORE 2 ENTRIES IN TX FIFO yes
STORE 1 ENTRY IN TX FIFO
SET BLOCK LENGTH
BLOCK LENGTH > 1?
no
STORE BLOCK LENGTH IN TX FIFO
Figure 10.4.1 Example flow for a transmit operation. The operations written with the courier font are not to be performed on the UART, but may involve TMPR3916 programming or only software operations.
10.4.2
Receiver programming
In case of a reception operation, the flow of a simple driver could be like the one depicted in Figure 10.4.2. Here the parameters used to program the UART are: * * * * * * 8 bit data length 1 stop bit even parity MSB first RTS hardware flow control Software operates in polling mode
10-22
Preliminary
Chapter 10 Asynchronous Serial Interface (UART)
START
TMPR3916 CCR REGISTER & MUX CONFIGURATION
Line Control Register: LSBF = 0 UEPS = 1 UPEN = 1 (Sets MSB first, 8 bit tx, etc)
yes
BLOCK LENGTH > 0?
Stop UART Reset (SIFCR) RFRST = 0 FRSTEW = 0
BLOCK LENGTH = BLOCK LENGTH - 1
0
Check RFDN (number of entries in RX FIFO) in the Interrupt Status Register
Check Interrupt Register for Frame, Parity, Overrun or Time Out errors
no errors
Flow Control Register RCS = 1 RSDR = 0 RTSTL = 0001 enables RTS hardware, storing of received data, sets RTS trigger level to 1
Retrieve one entry from RX FIFO
no
Reset UART: (SIFCR) SWRST = 1 RFRST = 1 FRSTEW = 1
RECEPTION ENDS
errors
ERROR
Retrieve the first entry from the RX FIFO
1
Check RFDN (number of entries in RX FIFO) in Interrupt Status Register
1
0
STORE THE FIFO ENTRY AS BLOCK LENGTH IN A REGISTER OF TMPR3916F
Figure 10.4.2 Example flow for a receive operation. The operations written with the courier font are not to be performed on the UART, but may involve TMPR3916 programming or only software operations.
10-23
Preliminary
Chapter 10 Asynchronous Serial Interface (UART)
10-24
Preliminary
Chapter 11 Electrical Characteristics
11. Electrical Characteristics
11.1 DC Characteristics of TMPR3916
Parameter
Supply Voltage Operating Temperature Storage Temperature Soldering Temperature (Time: 10 s) Power Dissipation (Normal Mode) Operating Current Normal Mode Standby Mode
Symbol
VDD Ta TSTG TSOLDER PD IDD IDDS VIL VIH
Min
3.0 -40 -40 150 -0.3 0.7VDD 0.7VDD
Typ
3.3
Max
3.6 85 125 260 1200 333 500 0.2VDD 5.8 VDD+0.3 10 -10 10 0.4
Unit
V C C C mW mA A V V V A A A V V mA mA
Low Level Input Voltage High Level Input Voltage 5 V Tolerant Others Low Level Input Current Standard Input Buffer Input Buffer with Pull-up (1) High Level Input Current Low Level Output Voltage High Level Output Voltage Output Current 4 mA Buffer (2) 8 mA Buffer (3)
IIL -10 -200 IIH VOL VOH IOL 4 8 -10 2.4
(1) The following inputs have an integrated pull-up resistance: VSYNC, HSYNC, DOTCLK, DREQ0, RESET, EXT0, EXT1, EXT2, NMI, dbge, dreset, BUSERR, ACK, RXCAN0, RXCAN1, PIO16, PIO18, PIO19, PIO21, PIO22, PIO23, PIO25, PIO26, PIO27, PIO29 (2) The following outputs are 4mA buffer outputs: TXCAN1, TXCAN0, HDISP, VSYNC, HSYNC, DOTCLK, PIO29, PIO28, PIO27, PIO26, PIO25, PIO24, PIO23, PIO22, PIO21, PIO20, PIO19, PIO18, PIO17, PIO16, PIO15, PIO14, PIO13, PIO12, PIO11, PIO10, PIO9, PIO8, PIO7, PIO6, PIO5, PIO4, PIO3, PIO2, PIO1, PIO0 (3) The following outputs are 8mA buffer outputs: A26, A25, A24, A23, A22, A21, A20, A19, A18, A17, A16, A15, A14, A13, A12, A11, A10, A9, A8, A7, A6, A5, A4, A3, A2, RD, WR, LAST, BSTART, BURST, CKE, WE, BE3, BE2, BE1, BE0, DREQ0, DACK0, SYSCLK, RAS, CAS, CS5, CS4, CS3, CS2, CS1, CS0, dclk, pcst2, pcst1, pcst0, sdao, D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15, D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30, D31
11-1
Preliminary
Chapter 11 Electrical Characteristics
11.2 Power Up Sequence
VDD PLLOFF* PLLCircuit Output CLKEN Output Clock External Reset A26 Value(1) tResetHold Internal Reset Note 1: A26 stabilization determined by RC delay Consider load on A26 for selection of pull-up/pull-down value tResetIntDelay tA26Sample tstaOSC tstaPLL
Figure 11.2.1 Waveform for TMPR3916's Power-up Sequence
Parameter
Oscillator Starting Time PLL Starting Time Reset Hold Time A26 Sample Time Initial Delay After Reset
(2)
Symbol
tstaOSC tstaPLL tResetHold tA26Sample tResetIntDelay
Min
25 1000
Typ
500
Max
500 4 1050
Unit
s s cycles (1) cycles (1) cycles (1)
(1) Cycle means one systemcycle of TMPR3916. (at 60 MHz one cycle is 16,7 ns) (2) Determined by external oscillator.
11-2
Preliminary
Chapter 11 Electrical Characteristics
11.3 Crystal Oscillator
An example of application circuit:
TMPR3916
XTAL1 RFB XTAL2
Xtal
Rd COUT1
CIN COUT2
LOUT
Figure 11.3.1 Connecting Crystal Oscillator
Parameter
Oscillator Frequency
(1)
Symbol
fOSC fSYS tstaOSC n
Min
6.5
Typ
7.5 500 8
Max
8.5 60.0
Unit
MHz MHz s
System Clock Frequency Oscillator Starting Time (2) Phase-Locked-Loop Multiplier (fSYS = n * fOSC)
(1) Restricted by the PLL input frequency capture range. (2) Determined by external oscillator.
11-3
Preliminary
Chapter 11 Electrical Characteristics
11.4 View DAC
DC Characteristics: Parameter
Resolution (Each DAC) Accuracy (Each DAC) Integral Linearity Error Differential Linearity Error Analog Output Current White Level White Level from Black Level Black Level Blank Level LSB Size Voltage-reference Input Current Stand-by Current IL DL
Symbol
Min

Typ
8 (1) 1/2 1/2 19.05 17.61 1.44 0.00 69.06 1.66 0.00
Max

Unit
Bits LSB LSB mA mA mA mA A mA mA
(1) Only upper six bits are used in TMPR3916, lower two bits are wired to zero AC Characteristics: Parameter
Clock Rate Clock Cycle Time Analog Output Full Scale Delay Full Scale Rise/Fall Time (10% to 90%) Glitch Impulse Power Supply Current IAA
Symbol
fmax tck tOD tOR
Min
5.72
Typ
1.8 0.78 32.5
Max
175 70
Unit
MHz ns ns ns pV - sec mA
Connectivity of ViewDAC:
TMPR3916
D V C C D G N D A G N D 4 A G N D 3 A G N D 2 V R E F V B S F S A D J R O U T A V C C 3 G O U T A V C C 2 B O U T A V C C 1 A G N D 1
0.1
0.1 0.1
0.1 3.3 V
3.3 k 0.1
745
37.5
37.5
37.5
10 10
1.235 V
RGB Output
* To reduce the noise, please place Ceramic Capacitors of 0.1uF between DVCC/DGND, AVCC3/AGND3, AVCC2/AGND2 and AVCC1/AGND1 as close as possible to the pads * Use seperate ground lines/planes for the digital and the analog ground in order to avoid analog ground level shift as a result of the current through the DGND terminal
Figure 11.4.1 Applying External Connectivity for Digital/Analog Converter
11-4
Preliminary
Chapter 11 Electrical Characteristics
11.5 Standby Mode Timing
To resume the PLL circuit operations, set the PLLOFF* pin to "High" and the CLKEN pin to high. At that time, a period of 500 s is required for the PLL circuit oscillation to stabilize. The following diagram shows the corresponding timing:
SYSCLK CLKEN PLLOFF* PLLSTOP
min 500 s
PLL oscillation
Figure 11.5.1 Standby Mode Waveform
11.6 Boot Device
By using the following application circuit, the user can choose between 16 bit and 32 bit boot device.
VSS Jumper VCC R = 47 K A26 TMPR3916 Memory Device Jumper connected to ... VCC => Boot by 16 Bit device VSS => Boot by 32 Bit device
Figure 11.6.1 Applying External Boot Mode Selection Circuit
11-5
Preliminary
Chapter 11 Electrical Characteristics
11.7 SDRAM Timing
Designing the SDRAM interface the following guidelines should be considered: * * SDRAM signals should be routed using a comparable wire-length for each interface signal capacitive load mismatches between different interface signals should be avoided
For the following electrical specification of the TMPR3916F external bus interface, balanced loads and equal wiring lengths of the interface signals are assumed. write access
t CR SYSCLK t CF SYSCLK
read access
A[31:0] BE[3:0] Dout[31:0] WE RAS, CAS tDOS tDOH
A[31:0] BE[3:0] sample point Din[31:0] WE RAS,CAS tDIS tDIH
Figure 11.7.1 SDRAM Interface Timing Diagram
Parameter
Output Setup Time Output Hold Time Input Setup Time Input Hold Time Clock Rise Time Clock Fall Time Load on Interface Signals
Symbol
tDOS tDOH tDIS tDIH tCR tCF CIF
Min
4.5 2.5 3,5 1.5
Typ

Max
4.0 4.0 30
Unit
ns ns ns ns ns ns pF
11-6
Preliminary
Chapter 11 Electrical Characteristics
11.8 ROM / SRAM Timing
SYSCLK CS
A BE
RD D*
tAOD
Sample Point Cycle is determined by RWT setting
tDIS
tAOH tDIH
tAOH
* Driven by the external memory device
Figure 11.8.1 ROM/Flash/SRAM Interface Timing Diagram (Read)
SYSCLK CS
A
BE WR
D* tACW tAOD tDOD
* Driven by TMPR3916F Write Hold Time is determined by RWT setting
tAOH
tAOH
tDOH
Figure 11.8.2 ROM/Flash/SRAM Interface Timing Diagram (Write)
Parameter
Address, Control Output Drive Time Data Output Drive Time Address, Control Output Hold Time Data Output Hold Time Address to CS or WR1 Data Input Setup Time Data Input Hold Time Load on Interface Signals
Symbol
tAOD tDOD tAOH tDOH tACW tDIS tDIH CIF
Min
2,0 2,0 0 3 2
Typ

Max
12 12,5 30
Unit
ns ns ns ns ns ns ns pF
1
Assumes balanced loads on WR, CS and Address pins.
11-7
Preliminary
Chapter 11 Electrical Characteristics
11.9 External Slave
Write timing:
tEOS1 SYSCLK CS A[31:0] BE[3:0] Dout[31:0] BSTART LAST WR ACK tEOS2 tEIS2 tEIH2 tEOH2 tEOH1
Figure 11.9.1 Timing Diagram for Write Access to External Slave Initiated by TMPR3916
Parameter
Output Setup Time of CS, A, BE, D Output Hold Time of CS, A, BE, D Output Setup Time of BSTART, LAST, WR, DACK Output Hold Time of BSTART, LAST, WR, DACK Input Setup Time of ACK Input Hold Time of ACK Load on Interface Signals
Symbol
tEOS1 tEOH1 tEOS2 tEOH2 tEIS2 tEIH2 CIF
Min
4.0 2.0 4.0 2.0 6.0 2.0
Typ

Max
30
Unit
ns ns ns ns ns ns pF
11-8
Preliminary
Chapter 11 Electrical Characteristics
Read timing:
sample point SYSCLK CS A[31:0] BE[3:0] Din[31:0] BSTART LAST WR ACK tEIS1 tEIH1
Figure 11.9.2 Timing Diagram for Read Access to External Slave Initiated by TMPR3916
Parameter
Input Setup Time of D[31:0] Input Hold Time of D[31:0] Load on Interface Signals
Symbol
tEIS1 tEIH1 CIF
Min
4.0 2.0
Typ

Max
30
Unit
ns ns pF
DMA Timing:
tMIS SYSCLK tMIH
DREQ
DACK tMOS tMOH
Figure 11.9.3 Timing Diagram for DMA Request
Parameter
Output Setup Time of DACK Output Hold Time of DACK Input Setup Time of DREQ Input Hold Time of DREQ Load on Interface Signals
Symbol
tMOS tMOH tMIS tMIH CIF
Min
5.0 2.0 6.0 2.0
Typ

Max
30
Unit
ns ns ns ns pF
11-9
Preliminary
Chapter 11 Electrical Characteristics
11.10 External Interrupts and NMI
The external interrupts (EXT0, EXT1, EXT2) and the NMI can be applied asynchronous to the system clock. All interrupt inputs are low active. Parameter
Length of Asynchronous Interrupt
Symbol
tIRQL
Min
2
Typ
Max
Unit
cycles (1)
(1) Cycle means one system cycle of TMPR3916 (at 60 MHz one cycle is 16.67 ns)
11.11 General Purpose I/O (PORT Module)
The inputs to the general purpose I/Os can be applied asynchronous to the system clock. Parameter
Length of Input Signal Sample Frequency
Symbol
tGPL fGPS
Min
10
Typ
7.5
(2)
Max

Unit
cycles (1) MHz
(1) Cycle means one system cycle of TMPR3916 (at 60 MHz one cycle is 16.67 ns) (2) at 60 MHz system clock
11-10
Preliminary
Chapter 11 Electrical Characteristics
11.12 TXSEI Timing
tCR tCF
1/fSEI
SCLK (SPOL=0) SCLK (SPOL=1)
tMOD tMOH
valid valid
TX (output)
tMIS
valid
RX (input)
valid
valid
valid
SS (output)
tSSOL
tMIH
Figure 11.12.1 Timing Diagram for TXSEI Timing (Master, SPHASE = 0)
tCR tCF
1/fSEI
SCLK (SPOL=0) SCLK (SPOL=1)
tMOD tMOH
valid valid
TX (output)
tMIS
valid
RX (input)
valid
valid
valid
tMIH
SS (output)
tSSOL
Figure 11.12.2 Timing Diagram for TXSEI Timing (Master, SPHASE = 1)
11-11
Preliminary
Chapter 11 Electrical Characteristics
Parameter
SEI Clock Frequency SEI Clock Rise Time SEI Clock Fall Time Master Data in Setup Time Master Data in Hold Time Master Data Out Drive Time Master Data Out Hold Time Slave Select Output Lead Time Load on SEI Interface Signals
Symbol
fSEI tCR tCF tMIS tMIH tMOD tMOH tSSOL CIF
Min
20 5 0 1
Typ

Max
15
(1)
Unit
MHz ns ns ns ns ns ns cyc(2) pF
12 12 20 50
(1) At 60 MHz system clock. In general: 1/4 of the system clock. (2) System cycles, means 16.67 ns at 60 MHz clock frequency.
1/fSEIS
SCLK (SPOL=0) SCLK (SPOL=1)
tSOD tSOH
valid valid
RX (output)
valid
tSIS
TX (input)
valid
valid
valid
tCTDT tSIH
SS (output)
tSSDV
Figure 11.12.3 Timing Diagram for TXSEI Timing (Slave, SPHASE = 0)
11-12
Preliminary
Chapter 11 Electrical Characteristics
1/fSEIS
SCLK (SPOL=0) SCLK (SPOL=1)
tSOD tSOH
valid valid
RX (output)
invalid
tSIS
tSIH
valid
TX (input)
valid
tCTDT
SS (output)
tSSDV
Figure 11.12.4 Timing Diagram for TXSEI Timing (Slave, SPHASE = 1)
Parameter
Slave Mode SEI Clock Frequency Clock to Data Valid Time Clock to Data Invalid Time Slave Data in Setup Time Slave Data in Hold Time Slave Select to Data Valid Time Slave Select to Clock Consecutive Transfer Delay Time Load on SEI Interface Signals
(2)
Symbol
fSEIS tSOD tSOH tSIS tSIH tSSDV tSSTC tCTDT CIF
Min
0 20 5 3/fSYS 1/fSEIS
Typ

Max
7.25 (1) 20 50 50
Unit
MHz ns ns ns ns ns ns ns pF
(1) At 60 MHz system clock. In general: 1/8 of the system clock frequency. (2) fSYS refers to the TMPR3916 system clock (usually 60 MHz). (3) For SPHASE = 1 the slave does not require to be deselected between consecutive transfers.
11-13
Preliminary
Chapter 11 Electrical Characteristics
11-14
Preliminary
Chapter 12 Package
12. Package
12.1 Pin Assignment
156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105
AN39GND VSS
PLLOFF AN39VDD
CLKEN
VDD3 XTAL2
XTAL1 VSS3
PIO10
PIO11 PIO12
PIO13 PIO14
PIO15 PIO16
PIO17 PIO18
PIO19 PIO20
PIO21 VDD3
PIO4 VDD3
VDD VSS2
VSS3
PIO9 VSS2
157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208
VSS3
PIO0 PIO1
PIO2
PIO3
PIO5
PIO6 VSS
PIO7
PIO8
VDD VSS
VDD
VSS
D8
D7 D6
D5 D4
D3 D2
D1
D0
D9 D10 D11 D12 D13 D14 VSS D15 D16 D17 D18 VDD VSS2 D19 D20 D21 VSS3 VDD3 D22 VSS D23 D24 D25 D26 D27 D28 D29 VDD D30 VSS D31 A2 A3 A4 A5 A6 A7 A8 VSS3 VDD3 VSS A9 VSS2 VDD A10 A11 A12 A13 A14 A15 A16 A17
TMPR3916F TOP VIEW
VDD VSS PIO22 PIO23 PIO24 PIO25 PIO26 PIO27 VSS2 VDD PIO28 PIO29 DOTCLK HSYNC VSYNC HDISP VSS dreset sdi dbge sdao pcst0 pcst1 pcst2 dclk VDD3 VSS3 VSS RXCAN0 TXCAN0 RXCAN1 TXCAN1 VDD VSS VSS2 DGND DVCC AVCC1 AGND3 AVCC2 VREF VBS AGND2 FSADJ AGND1 BOUT GOUT ROUT AGND5 AGND4 AVCC3 Not Connected
104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53
NMI
RD
CS5
CS4
CS3
CS2
CS1
BUSERR DREQ0
A19 VSS2
VDD A20
VDD
VDD VSS
CS0
50
BE3 BE2
BE1
BE0
A18
A21 A22
A23 A24
A25 A26
VDD
VDD
51
SYSCLK RAS
BURST
RESET VSS
VDD3
VSS3 LAST
EXT2
BSTART
DACK0
EXT1 EXT0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VSS2
31
32
33
34
35
36
37
38
39
40
41
42
43
VSS2
44
45
46
47
48
49
Figure 12.1.1 TMPR3916F's Pin Assignment
52
1
2
3
4
5
6
7
8
9
test0
CKE WE
ACK
CAS
WR VSS
12-1
Preliminary
Chapter 12 Package
The following table divides the different pins into functional groups. TMPR3916F provides pins, which have a shared functionality. Therefore you can find one and the same pin up to three times in different groups (like PIO18/TX(SEI)/TX(SIO0) pin). Classification
CORE A[25:20] A[19:18] A[17:10] A[9] A[8:2] BE[3:0]* D[31] D[30] D[29:23] D[22] D[21:19] D[18:15] D[14:9] D[8:4] D[3:0] Control Signals RD* WR* LAST* BSTART* BURST* BUSERR* ACK* RESET* Clock Signals XTAL1 XTAL2 SYSCLK PLLOFF* CLKEN SDRAM CS1* CS0* RAS* CAS* CKE WE* MEMC CS5* CS4* CS3* CS2* GDC HSYNC* VSYNC*/CSYNC* HDISP DOTCLK PIO0/Digital B Out[0] PIO1/Digital B Out[1] PIO2/Digital B Out[2] PIO3/Digital B Out[3] PIO4/Digital B Out[4] 151 152 39 155 156 49 50 40 41 21 22 42 46 47 48 91 90 89 92 134 133 132 131 130 I O O I I O O O O O O O O O O I/O I/O O I/O I/O I/O I/O I/O I/O low high low low low low high low low low low low low low high 12 13 18 19 20 31 37 27 O O O O O I I I low low low low low low low low
Pin Name
A[26] / BOOT16 11 10 ~ 5 2~1 208 ~ 201 198 194 ~ 188 23 ~ 26 187 185 183 ~ 177 175 172 ~170 167 ~ 164 162 ~ 157 145 ~ 141 138 ~ 135
Pin No.
I/O
I/O O O O O O O I/O I/O I/O I/O I/O I/O I/O I/O I/O
Level Active
low
12-2
Preliminary
Chapter 12 Package
Classification
GDC
Pin Name
PIO5/Digital B Out[5] PIO6/Digital G Out[1] PIO7/Digital G Out[2] PIO8/Digital G Out[3] PIO9/Digital G Out[4] PIO10/Digital G Out[5] PIO11/Digital R Out[1] PIO12/Digital R Out[2] PIO13/Digital R Out[3] PIO14/Digital R Out[4] PIO15/Digital R Out[5] ROUT GOUT BOUT VBS VREF FSADJ 127 126 124 123 122 119 118 117 116 115 113 57 58 59 63 64 61 32 33 73 74 75 76 110 111 112 109 102 93 94 97 98 99 100 101 102 107 108 109 110 111 112 93 94 97 98 99 100 101 102 107 108 109 110
Pin No.
I/O
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O A. O A. O A. O
Level Active

DMAC TXCAN
DREQ0* DACK0* TX(CAN1) RX(CAN1) TX(CAN0) RX(CAN0)
I O O I O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
low low low low low low low low
TXSEI
PIO18/TX(SEI)/TX(SIO0) PIO17/RX(SEI)/RX(SIO0) PIO16/CLK(SEI)/CLK(SIO0) PIO19/SSI*(SEI)/CLK(SIO1) PIO22/SSO*(SEI)/RTS*(SIO1)
UART
PIO29/TX(SIO3) PIO28/RX(SIO3) PIO27/CTS*(SIO2) PIO26/RTS*(SIO2) PIO25/TX(SIO2) PIO24/RX(SIO2) PIO23/CTS*(SIO1) PIO22/SSO*(SEI)/RTS*(SIO1) PIO21/TX(SIO1) PIO20/RX(SIO1) PIO19/SSI*(SEI)/CLK(SIO1) PIO18/TX(SEI)/TX(SIO0) PIO17/RX(SEI)/RX(SIO0) PIO16/CLK(SEI)/CLK(SIO0)
PORT
PIO29/TX(SIO3) PIO28/RX(SIO3) PIO27/CTS*(SIO2) PIO26/RTS*(SIO2) PIO25/TX(SIO2) PIO24/RX(SIO2) PIO23/CTS*(SIO1) PIO22/SSO*(SEI)/RTS*(SIO1) PIO21/TX(SIO1) PIO20/RX(SIO1) PIO19/SSI*(SEI)/CLK(SIO1) PIO18/TX(SEI)/TX(SIO0)
12-3
Preliminary
Chapter 12 Package
Classification
PORT
Pin Name
PIO17/RX(SEI)/RX(SIO0) PIO16/CLK(SEI)/CLK(SIO0) PIO15/Digital R Out [5] PIO14/Digital R Out [4] PIO13/Digital R Out [3] PIO12/Digital R Out [2] PIO11/Digital R Out [1] PIO10/Digital G Out [5] PIO9/Digital G Out [4] PIO8/Digital G Out [3] PIO7/Digital G Out [2] PIO6/Digital G Out [1] PIO5/Digital B Out [5] PIO4/Digital B Out [4] PIO3/Digital B Out [3] PIO2/Digital B Out [2] PIO1/Digital B Out [1] PIO0/ Digital B Out [0] 111 112 113 115 116 117 118 119 122 123 124 126 127 130 131 132 133 134 34 35 36 38
Pin No.
I/O
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I I
Level Active
low low low low
INTC
EXT2* EXT1* EXT0* NMI*
POWER
VDD VDD3 VSS
4, 15, 29, 44, 51, 72, 95, 104, 120, 140, 147, 168, 184, 200 16, 79, 106, 129, 153, 174, 196 14, 28, 45, 71, 77, 88, 103, 114, 125, 139, 148, 163, 176, 186, 197 3, 30, 43, 70, 96, 121, 146, 169, 199 17, 78, 105,128, 150, 173, 195 67 65 54 68 69 154 149 60 62 66 55 56 80 81 82 83 84 85 86 87 52 53 O O O O O I I I I
VSS2 VSS3 AVCC1 AVCC2 AVCC3 DVCC DGND AN39VDD AN39GND AGND1 AGND2 AGND3 AGND4 AGND5 DSU dclk pcst2 pcst1 pcst0 sdao/tpc dbge* sdi/dint* dreset* TEST Not Connected
(1)

low low low high
test0 N/C(1)
Recommendation: Connect unconnected pins to ground.
12-4
Preliminary
Chapter 12 Package
12.2 Pin Functions
Classification
CORE A[26:2]
Pin Name
Pin Function
Address signal output pins. The A26 pin has a special functionality. The level supplied to this pin is latched with the rising edge of the RESET* signal. The level determines whether to boot from a device with 16-bit or 32-bit width. Supplying "high" lets the TMPR3916F boot from a 16-bit device. Byte Enable output pins The byte enable signals are used to select the bytes within the word, which are accessed by the current write or read access. The following list shows the relationship between byte enable signals and the valid bytes on the data bus. BE*[0] low => D[7:0] valid BE*[1] low => D[15:8] valid BE*[2] low => D[23:16] valid BE*[3] low => D[31:24] valid Data input/output pins The RD* signal is asserted during a read access to the external bus interface. The WR* signal is asserted during a write access to the external bus interface. The LAST* signal is asserted if the final data of the current bus operation is read or written. The BSTART* signal is asserted for one cycle at the beginning of an external bus interface access. The BURST* signal indicates that the current access is a burst access. Bus Error input pin. If an error occurs during the current transaction the external device has the opportunity to signal this event to the TMPR3916F by asserting the BUSERR* signal. Thereupon the TMPR3916F will finish the access and will create a bus-error exception. Acknowledge signal input pin. During a read access the external device acknowledges datatransfers of a transaction by asserting the ACK* signal. The data on the external bus interface will be sampled on the rising edge of system clock. During a write access the external device signals the TMPR3916F that the data was captured by asserting the ACK* signal. The TMPR3916F will complete the transaction. If a low level is applied to the RESET* signal the chip will go into the reset state. Input pin for the crystal. Feedback output pin for the crystal. Output of system clock, which is the reference clock for bus operation. Master clock switching pin. Inputting a "High" signal to this pin uses the built-in PLL circuit as the master clock. Master clock frequency is eight times the external clock. Inputting a low signal to this pin halts the built-in PLL circuit oscillation and uses the external clock as master clock. The clock enable pin enables supply of crystal input to internal PLL. This signal is high active. Chip select 1* signal for the external SDRAM device. Chip select 0* signal for the external SDRAM device. The three signals row access strobe (RAS*), column access strobe (CAS*) and write enable (WE*) are used to supply the SDRAM with commands. The clock enable pin is an output to SDRAM used for power saving purposes.
BE[3:0]*
D[31:0] RD* WR* LAST* BSTART* BURST* BUSERR*
ACK*
RESET* Clock Generator XTAL1 XTAL2 SYSCLK PLLOFF*
CLKEN SDRAM CS1* CS0* RAS* CAS* WE* CKE
12-5
Preliminary
Chapter 12 Package
Classification
MC CS5* CS4* CS3* CS2* GDC HSYNC* VSYNC*/CSYNC*
Pin Name
Pin Function
The chip select signal 5 will be asserted if an access to the address range specified in the RCCR5 register will take place. The chip select signal 4 will be asserted if an access to the address range specified in the RCCR4 register will take place. The chip select signal 3 will be asserted if an access to the address range specified in the RCCR3 register will take place. The chip select signal 2 will be asserted if an access to the address range specified in the RCCR2 register will take place. Horizontal sync signal input/output pin. Vertical sync signal input/output pin or the composite sync signal output pin. The composite sync signal is the logic EX-NOR (exclusive nor) operation on signals HSYNC* and VSYNC* While the viewable area of the current line is output by the GDC the HDISP is set to logic one. Data can be read with one cycle latency to this signal. Dot clock input/output pin. The dot clock is the reference clock for the display. This clock is either input to or output by the TMPR3916F. The general purpose input/output signals PIO11 to PIO15 (5bit) can be switched in that way that the red intensity of the current pixel is output. PIO15/Digital R Out[5] is the MSB.
HDISP
DOTCLK
PIO15/Digital R Out[5] PIO14/Digital R Out[4] PIO13/Digital R Out[3] PIO12/Digital R Out[2] PIO11/Digital R Out[1] PIO10/Digital G Out[5] PIO9/Digital G Out[4] PIO8/Digital G Out[3] PIO7/Digital G Out[2] PIO6/Digital G Out[1] PIO5/Digital B Out[5] PIO4/Digital B Out[4] PIO3/Digital B Out[3] PIO2/Digital B Out[2] PIO1/Digital B Out[1] PIO0/Digital B Out[0] ROUT GOUT BOUT
The general purpose input/output signals PIO6 to PIO10 (5 bit) can be switched in that way that the green intensity of the current pixel is output. PIO10/Digital G Out[5] is the MSB.
The general purpose input/output signals PIO0 to PIO5 (6 bit) can be switched in that way that the blue intensity of the current pixel is output. PIO5/Digital B Out[5] is the MSB.
Output pins for the three primary color video (analog) signals used as color source for display. ROUT is the red video signal output pin, GOUT the green and BOUT the blue. All these signal are analog signals output by the VIEWDAC. This terminal is used for noise rejection of DAC's current adjustment bias. It is recommended to connect a capacitance of 0.1*F to the ground. External voltage reference-bias input for the digital-to-analog converter. Current-mirror output. This pin is used to set the current level in the DAC outputs via an internal current-mirror. This pin is usually connected to ground via a 745 Ohm resistor. External DMA request signal. DMA acknowledge signal output pin. Transmit pin of CAN channel 1 Receive pin of CAN channel 1 Transmit pin of CAN channel 0 Receive pin of CAN channel 0 In master mode this pin is the data output of the SEI interface. In slave mode this is the data input pin of the SEI interface. In master mode this pin is the data input pin of the TXSEI device. In slave mode this pin is the data output. In master mode the clock is output during transmission from the TXSEI module. In slave mode the clock is received from the device the TMPR3916F is communicating with.
VBS
VREF FSADJ
DMAC TXCAN
DREQ0 DACK0 TX(CAN1) RX(CAN1) TX(CAN0) RX(CAN0)
TXSEI
PIO18/TX(SEI)/TX(SIO0) PIO17/RX(SEI)/RX(SIO0) PIO16/CLK(SEI)/CLK(SIO)
12-6
Preliminary
Chapter 12 Package
Classification
TXSEI
Pin Name
PIO19/SSI*(SEI)/CLK(SIO1)
Pin Function
When the TXSEI module is configured as a slave the SSI* (slaveselect-input) signal shows that the TXSEI module is accessed in the current transfer. In master mode this pin can be used to check the bus for a second master on the bus. By definition more than one master is not allowed because such a configuration might damage the circuits! During master mode the SSO* (slave-select output) is used to enable the outputs of an SEI device connected to the TMPR3916F. Serial data transmit (output) pin.
PIO22/SSO*(SEI)/RTS*(SIO1) UART PIO29/TX(SIO3) PIO25/TX(SIO2) PIO21/TX(SIO1) PIO18/TX(SEI)/TX(SIO0) PIO28/RX(SIO3) PIO24/RX(SIO2) PIO20/RX(SIO1) PIO17/RX(SEI)/RX(SIO0) PIO26/RTS*(SIO2) PIO22/SSO*(SEI)/RTS*(SIO1) PIO27/CTS*(SIO2) PIO23/CTS*(SIO1) PIO19/SSI*(SEI)/CLK(SIO1) PIO16/CLK(SEI)/CLK(SIO0) PORT INTC PIO[29:0] EXT[2:0]* NMI*
Serial data receive (input) pin.
Request to send signal output pin. Clear to send signal output pin. UART clock output for synchronous transfer mode 30-bit parallel I/O port pins. Interrupt request signal input pins. Non-maskable interrupt signal input pin. If this signal is asserted the TX39 core jumps to the non-maskableinterrupt service routine. Debug clock This pin outputs a clock for a real time debug system. PC trace status Outputs PC trace status information and the mode of the serial monitor bus. Serial data and address Output / target PC Debugger enable The external real time debug system signals to the DSU by asserting this pin, that it is connected. Serial data input / debug interrupt When DSU mode is not used, this pin must be tied to High. Debug reset A reset input for a real-time debug system. When dreset* is asserted, the debug support unit (DSU) is initialized. This pin is used for manufacturing test purposes. For regular operation this pin must be tied to zero. Otherwise the TMPR3916F and connected devices may be damaged.
DSU1
dclk pcst[2:0]
sdao/tpc dbge*
sdi/dint* dreset*
TEST
test0
1
If the DSU interface is not utilized, tie sdi/dint* to VCC using a 47 K resistor; leave dreset* and dgbe* pins open.
12-7
Preliminary
Chapter 12 Package
12-8
Preliminary
Appendix A Register Overview of TMPR3916
Appendix A.
Classification
UART
Register Overview of TMPR3916
Address
1C00 0000H 1C00 0004H 1C00 0008H 1C00 000CH 1C00 0010H 1C00 0014H 1C00 0018H 1C00 001CH 1C00 0020H 1C00 0040H 1C00 0044H 1C00 0048H 1C00 004CH 1C00 0050H 1C00 0054H 1C00 0058H 1C00 005CH 1C00 0060H 1C00 0080H 1C00 0084H 1C00 0088H 1C00 008CH 1C00 0090H 1C00 0094H 1C00 0098H 1C00 009CH 1C00 00A0H 1C00 00C0H 1C00 00C4H 1C00 00C8H 1C00 00CCH 1C00 00D0H 1C00 00D4H 1C00 00D8H 1C00 00DCH 1C00 00E0H
Register Name
SILCR0 SIDICR0 SIDISR0 SISCISR0 SIFCR0 SIFLCR0 SIBGR0 SITFIFO0 SIRFIFO0 SILCR1 SIDICR1 SIDISR1 SISCISR1 SIFCR1 SIFLCR1 SIBGR1 SITFIFO1 SIRFIFO1 SILCR2 SIDICR2 SIDISR2 SISCISR2 SIFCR2 SIFLCR2 SIBGR2 SITFIFO2 SIRFIFO2 SILCR3 SIDICR3 SIDISR3 SISCISR3 SIFCR3 SIFLCR3 SIBGR3 SITFIFO3 SIRFIFO3 SEMCR SECR0 SECR1 SEFS SESS SESR SEDR SERS TIMER TITR PWMVAL RCCR2 RCCR3 RCCR4 RCCR5
Function
SIO Control Register (CH0) SIO Interrupt Control Register (CH0) SIO Interrupt Status Register (CH0) SIO Status Change Register (CH0) SIO FIFO Control Register (CH0) SIO Flow Control Register (CH0) SIO Baud Rate Control Register (CH0) SIO Transmit FIFO Register (CH0) SIO Receive FIFO Register (CH0) SIO Control Register (CH1) SIO Interrupt Control Register (CH1) SIO Interrupt Status Register (CH1) SIO Status Change Register (CH1) SIO FIFO Control Register (CH1) SIO Flow Control Register (CH1) SIO Baud Rate Control Register (CH1) SIO Transmit FIFO Register (CH1) SIO Receive FIFO Register (CH1) SIO Control Register (CH2) SIO Interrupt Control Register (CH2) SIO Interrupt Status Register (CH2) SIO Status Change Register (CH2) SIO FIFO Control Register (CH2) SIO Flow Control Register (CH2) SIO Baud Rate Control Register (CH2) SIO Transmit FIFO Register (CH2) SIO Receive FIFO Register (CH2) SIO Control Register (CH3) SIO Interrupt Control Register (CH3) SIO Interrupt Status Register (CH3) SIO Status Change Register (CH3) SIO FIFO Control Register (CH3) SIO Flow Control Register (CH3) SIO Baud rate Control Register (CH3) SIO Transmit FIFO Register (CH3) SIO Receive FIFO Register (CH3) SEI Master Control Register SEI Control Register 0 SEI Control Register 1 SEI Inter Frame Space Register SEI Slave Select Space Register SEI Status Register SEI Data Register SEI Read Start Register Free running counter of periodic timers Timer Interval Time Register compare value for PWM counter ROM Channel Control Register 2 ROM Channel Control Register 3 ROM Channel Control Register 4 ROM Channel Control Register 5
TXSEI
1C00 8000H 1C00 8004H 1C00 8008H 1C00 800CH 1C00 8010H 1C00 8014H 1C00 8018H 1C00 801CH
TIMER
1C01 0000H 1C01 0004H 1C01 0008H
MEMC
1C02 0008H 1C02 000CH 1C02 0010H 1C02 0014H
A-1
Preliminary
Appendix A Register Overview of TMPR3916
Classification
SDRAMC
Address
1C02 8000H 1C02 8004H 1C02 8008H 1C02 800CH
Register Name
DCCR DCBA DCAM DCTR PA PACR PAL PALMX PAMSK PAMUX IRQR IMASKR ILEXT DCR SARA SARB SARC SARD MWRA MWRB MWRC MWRD HTN HTND HDSER HDSERD HCR HSWR VCR VSWR VDSR VDSRD VDER VDERD CPLTA0 ... CPLTA255 CPLTB0 ... CPLTB255 CPLTC0 ... CPLTC15 CPLTD0 ... CPLTD15 ODR0 CCR0 CER0 CSR0 SAR0 DAR0 BCR0 ODR1 Configuration Register Base Address Register Address Mask Register Timing Register PORT Data Register PORT Control Register PORT Interrupt Flag
Function
PORT
1C03 0000H 1C03 0004H 1C03 0008H 1C03 000CH 1C03 0010H 1C03 0014H
PORT Edge Select for Interrupt PORT Interrupt Enable Output Select for PORT/ TXSEI/ UART Interrupt Request Register Interrupt Mask Register External Interrupt Detection Register Display Control Register Start Address Register Layer A Start Address Register Layer B Start Address Register Layer C Start Address Register Layer D Memory Width Register Layer A Memory Width Register Layer B Memory Width Register Layer C Memory Width Register Layer D Horizontal Transfer Number Horizontal Transfer Number Layer D Horizontal Display Start Register Horizontal Display Start Register Layer D Horizontal Cycle Register Horizontal Synchronous Pulse Width Vertical Cycle Register Vertical Synchronous pulse Width Vertical Display Start Register Vertical Display Start Register layer D Vertical Display End Register Vertical Display End Register layer D Color Palette Register layer A number 0 ... Color Palette Register layer A number 255 Color Palette Register layer B number 0 ... Color Palette Register layer B number 255 Color Palette Register layer C number 0 ... Color Palette Register layer C number 15 Color Palette Register layer D number 0 ... Color Palette Register layer D number 15 Operation Definition Register 0 Channel Control Register 0 Channel Error Register 0 Channel Status Register 0 Source Address Register 0 Destination Address Register 0 Byte Control Register 0 Operation Definition Register 1
INTC
1C04 0000H 1C04 0004H 1C04 0008H
GDC
1C05 0000H 1C05 0010H 1C05 0014H 1C05 0018H 1C05 001CH 1C05 0020H 1C05 0024H 1C05 0028H 1C05 002CH 1C05 0030H 1C05 0034H 1C05 0038H 1C05 003CH 1C05 0040H 1C05 0044H 1C05 0048H 1C05 004CH 1C05 0050H 1C05 0054H 1C05 0058H 1C05 005CH 1C05 0800H ... 1C05 0BFCH 1C05 0C00H ... 1C05 0FFCH 1C05 0180H ... 1C05 01BCH 1C05 01C0H ... 1C05 01FCH
DMAC
1C06 0000H 1C06 0001H 1C06 0002H 1C06 0003H 1C06 0004H 1C06 0008H 1C06 000CH 1C06 0010H
A-2
Preliminary
Appendix A Register Overview of TMPR3916
Classification
DMAC
Address
1C06 0011H 1C06 0012H 1C06 0013H 1C06 0014H 1C06 0018H 1C06 001CH
Register Name
CCR1 CER1 CSR1 SAR1 DAR1 BCR1 DPRAM0 Channel Error Register 1
Function
Channel Control Register 1 Channel Status Register 1 Source Address Register 1 Destination Address Register 1 Byte Control Register 1 Mailbox RAM (CH0)
TXCAN
1C07 0000H ... 1C07 00F0H 1C07 0100H 1C07 0104H 1C07 0108H 1C07 010CH 1C07 0110H 1C07 0114H 1C07 0118H 1C07 011CH 1C07 0120H 1C07 0124H 1C07 0128H 1C07 012CH 1C07 0130H 1C07 0134H 1C07 0138H 1C07 013CH 1C07 0140H 1C07 0144H 1C07 0148H 1C07 014CH 1C07 0150H 1C07 0154H 1C07 0158H 1C07 015CH 1C07 8000H ... 1C07 80F0H 1C07 8100H 1C07 8104H 1C07 8108H 1C07 810CH 1C07 8110H 1C07 8114H 1C07 8118H 1C07 811CH 1C07 8120H 1C07 8124H 1C07 8128H 1C07 812CH 1C07 8130H 1C07 8134H 1C07 8138H 1C07 813CH 1C07 8140H 1C07 8144H
MC0 MD0 TRS0 TRR0 TA0 AA0 RMP0 RML0 LAM0 GAM0 MCR0 GSR0 BCR10 BCR20 GIF0 GIM0 MBTIF0 MBRIF0 MBIM0 CDR0 RFP0 CEC0 TSP0 TSC0 DPRAM1
Mailbox Configuration Register (CH0) Mailbox Direction Register (CH0) Transmit Request Set Register (CH0) Transmit Request Reset Register (CH0) Transmission Acknowledge Register (CH0) Abort Acknowledge Register (CH0) Receive Message Pending Register (CH0) Receive Message Lost Register (CH0) Local Acceptance Mask Register (CH0) Global Acceptance Mask Register (CH0) Master Control Register (CH0) Global Status Register (CH0) Bit Configuration Register 1 (CH0) Bit Configuration Register 2 (CH0) Global Interrupt Flag Register (CH0) Global Interrupt Mask Register (CH0) Mailbox Transmit Interrupt Flag Register (CH0) Mailbox Receive Interrupt Flag Register (CH0) Mailbox Interrupt Mask Register (CH0) Change Data Request (CH0) Remote Frame Pending Register (CH0) CAN Error Counter Register (CH0) Time Stamp Counter Prescaler (CH0) Time Stamp Counter (CH0) Mailbox RAM (CH1)
MC1 MD1 TRS1 TRR1 TA1 AA1 RMP1 RML1 LAM1 GAM1 MCR1 GSR1 BCR11 BCR21 GIF1 GIM1 MBTIF1 MBRIF1
Mailbox Configuration Register (CH1) Mailbox Direction Register (CH1) Transmit Request Set Register (CH1) Transmit Request Reset Register (CH1) Transmission Acknowledge Register (CH1) Abort Acknowledge Register (CH1) Receive Message Pending Register (CH1) Receive Message Lost Register (CH1) Local Acceptance Mask Register (CH1) Global Acceptance Mask Register (CH1) Master Control Register (CH1) Global Status Register (CH1) Bit Configuration Register 1 (CH1) Bit Configuration Register 2 (CH1) Global Interrupt Flag Register (CH1) Global Interrupt Mask Register (CH1) Mailbox Transmit Interrupt Flag Register (CH1) Mailbox Receive Interrupt Flag Register (CH1)
A-3
Preliminary
Appendix A Register Overview of TMPR3916
Classification
TXCAN
Address
1C07 8148H 1C07 814CH 1C07 8150H 1C07 8154H 1C07 8158H 1C07 815CH
Register Name
MBIM1 CDR1 RFP1 CEC1 TSP1 TSC1 CCR
Function
Mailbox Interrupt Mask Register (CH1) Change Data Request (CH1) Remote Frame Pending Register (CH1) CAN Error Counter Register (CH1) Time Stamp Counter Prescaler (CH1) Time Stamp Counter (CH1) Chip Configuration Register
CCR
1C08 0000H
A-4
Preliminary

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